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https://github.com/AsahiLinux/u-boot
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f0f3762cb7
Taking into account the Amlogic Family name starts with GX, including the GXBB, GXL and GXM SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2016 - Beniamino Galvani <b.galvani@gmail.com>
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*/
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#ifndef __GX_H__
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#define __GX_H__
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#define GX_FIRMWARE_MEM_SIZE 0x1000000
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#define GX_AOBUS_BASE 0xc8100000
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#define GX_PERIPHS_BASE 0xc8834400
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#define GX_HIU_BASE 0xc883c000
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#define GX_ETH_BASE 0xc9410000
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/* Always-On Peripherals registers */
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#define GX_AO_ADDR(off) (GX_AOBUS_BASE + ((off) << 2))
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#define GX_AO_SEC_GP_CFG0 GX_AO_ADDR(0x90)
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#define GX_AO_SEC_GP_CFG3 GX_AO_ADDR(0x93)
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#define GX_AO_SEC_GP_CFG4 GX_AO_ADDR(0x94)
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#define GX_AO_SEC_GP_CFG5 GX_AO_ADDR(0x95)
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#define GX_AO_MEM_SIZE_MASK 0xFFFF0000
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#define GX_AO_MEM_SIZE_SHIFT 16
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#define GX_AO_BL31_RSVMEM_SIZE_MASK 0xFFFF0000
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#define GX_AO_BL31_RSVMEM_SIZE_SHIFT 16
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#define GX_AO_BL32_RSVMEM_SIZE_MASK 0xFFFF
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/* Peripherals registers */
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#define GX_PERIPHS_ADDR(off) (GX_PERIPHS_BASE + ((off) << 2))
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/* GPIO registers 0 to 6 */
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#define _GX_GPIO_OFF(n) ((n) == 6 ? 0x08 : 0x0c + 3 * (n))
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#define GX_GPIO_EN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 0)
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#define GX_GPIO_IN(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 1)
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#define GX_GPIO_OUT(n) GX_PERIPHS_ADDR(_GX_GPIO_OFF(n) + 2)
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#define GX_ETH_REG_0 GX_PERIPHS_ADDR(0x50)
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#define GX_ETH_REG_1 GX_PERIPHS_ADDR(0x51)
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#define GX_ETH_REG_2 GX_PERIPHS_ADDR(0x56)
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#define GX_ETH_REG_3 GX_PERIPHS_ADDR(0x57)
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#define GX_ETH_REG_0_PHY_INTF BIT(0)
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#define GX_ETH_REG_0_TX_PHASE(x) (((x) & 3) << 5)
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#define GX_ETH_REG_0_TX_RATIO(x) (((x) & 7) << 7)
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#define GX_ETH_REG_0_PHY_CLK_EN BIT(10)
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#define GX_ETH_REG_0_INVERT_RMII_CLK BIT(11)
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#define GX_ETH_REG_0_CLK_EN BIT(12)
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/* HIU registers */
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#define GX_HIU_ADDR(off) (GX_HIU_BASE + ((off) << 2))
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#define GX_MEM_PD_REG_0 GX_HIU_ADDR(0x40)
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/* Ethernet memory power domain */
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#define GX_MEM_PD_REG_0_ETH_MASK (BIT(2) | BIT(3))
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/* Clock gates */
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#define GX_GCLK_MPEG_0 GX_HIU_ADDR(0x50)
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#define GX_GCLK_MPEG_1 GX_HIU_ADDR(0x51)
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#define GX_GCLK_MPEG_2 GX_HIU_ADDR(0x52)
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#define GX_GCLK_MPEG_OTHER GX_HIU_ADDR(0x53)
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#define GX_GCLK_MPEG_AO GX_HIU_ADDR(0x54)
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#define GX_GCLK_MPEG_0_I2C BIT(9)
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#define GX_GCLK_MPEG_1_ETH BIT(3)
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#endif /* __GX_H__ */
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