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e5cb6bd9a2
Patch "ARM: rmobile: Mark 4-64GiB as DRAM on Gen3" marked the entire
64bit DRAM space as cachable. On CortexA57, this might result in odd
side effects, where the CPU tries to prefetch from those areas and if
there is no DRAM backing them, CPU bus hang can happen.
This patch fixes it by generating the mem_map structure based on the
actual memory layout obtained from the DT, thus not marking areas
without any DRAM behind them as cachable.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Fixes:
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.. | ||
include/mach | ||
board.c | ||
cpu_info-r8a7740.c | ||
cpu_info-rcar.c | ||
cpu_info-sh73a0.c | ||
cpu_info.c | ||
emac.c | ||
Kconfig | ||
Kconfig.32 | ||
Kconfig.64 | ||
lowlevel_init.S | ||
lowlevel_init_ca15.S | ||
lowlevel_init_gen3.S | ||
Makefile | ||
memmap-gen3.c | ||
pfc-r8a7740.c | ||
pfc-r8a7790.h | ||
pfc-sh73a0.c | ||
timer.c |