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f51cdaf191
Currently, 83xx, 86xx, and 85xx have a lot of duplicated code dedicated to defining and manipulating the LBC registers. Merge this into a single spot. To do this, we have to decide on a common name for the data structure that holds the lbc registers - it will now be known as fsl_lbc_t, and we adopt a common name for the immap layouts that include the lbc - this was previously known as either im_lbc or lbus; use the former. In addition, create accessors for the BR/OR regs that use in/out_be32 and use those instead of the mismash of access methods currently in play. I have done a successful ppc build all and tested a board or two from each processor family. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Acked-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
84 lines
2.2 KiB
C
84 lines
2.2 KiB
C
/*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <common.h>
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#include <asm/fsl_lbc.h>
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void print_lbc_regs(void)
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{
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int i;
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printf("\nLocal Bus Controller Registers\n");
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for (i = 0; i < 8; i++) {
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printf("BR%d\t0x%08X\tOR%d\t0x%08X\n",
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i, get_lbc_br(i), i, get_lbc_or(i));
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}
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}
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void init_early_memctl_regs(void)
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{
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uint init_br1 = 1;
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#ifdef CONFIG_MPC85xx
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/* if cs1 is already set via debugger, leave cs0/cs1 alone */
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if (get_lbc_br(1) & BR_V)
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init_br1 = 0;
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#endif
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/*
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* Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
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* preliminary addresses - these have to be modified later
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* when FLASH size has been determined
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*/
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#if defined(CONFIG_SYS_OR0_REMAP)
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set_lbc_or(0, CONFIG_SYS_OR0_REMAP);
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#endif
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#if defined(CONFIG_SYS_OR1_REMAP)
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set_lbc_or(1, CONFIG_SYS_OR1_REMAP);
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#endif
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/* now restrict to preliminary range */
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if (init_br1) {
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set_lbc_br(0, CONFIG_SYS_BR0_PRELIM);
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set_lbc_or(0, CONFIG_SYS_OR0_PRELIM);
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#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
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set_lbc_or(1, CONFIG_SYS_OR1_PRELIM);
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set_lbc_br(1, CONFIG_SYS_BR1_PRELIM);
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#endif
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}
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#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
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set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
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set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
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#endif
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#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
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set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
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set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
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#endif
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#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
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set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
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set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
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#endif
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#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
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set_lbc_or(5, CONFIG_SYS_OR5_PRELIM);
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set_lbc_br(5, CONFIG_SYS_BR5_PRELIM);
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#endif
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#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
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set_lbc_or(6, CONFIG_SYS_OR6_PRELIM);
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set_lbc_br(6, CONFIG_SYS_BR6_PRELIM);
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#endif
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#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
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set_lbc_or(7, CONFIG_SYS_OR7_PRELIM);
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set_lbc_br(7, CONFIG_SYS_BR7_PRELIM);
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#endif
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}
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