Alexey Brodkin 5bea2becf3 arc: Update data accessors with use of memory barriers ... Memory barriers are proven to be a requirement for both compiler and real hardware to properly serialize access to critical data. For example if CPU or data bus it uses may do reordering of data accesses absence of memory barriers might easily lead to very subtle and hard to debug data corruptions. This implementation was heavily borrowed from up to date Linux kernel. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>		2016-06-13 14:38:05 +02:00
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cpu	arc: make sure _start is in the beginning of .text section	2015-04-10 18:45:34 +03:00
dts	axs103: add support of generic OHCI USB 1.1 controller	2015-12-21 23:29:04 +03:00
include/asm	arc: Update data accessors with use of memory barriers	2016-06-13 14:38:05 +02:00
lib	arc/cache: Flush & invalidate all caches right before enabling IOC	2016-06-13 14:38:05 +02:00
config.mk	arc: use more universal prefix for default CROSS_COMPILE	2015-05-13 13:44:25 +03:00
Kconfig	arc: cache - accommodate different L1 cache line lengths	2016-02-20 11:19:53 +03:00
Makefile	arc: introduce separate section for interrupt vector table	2015-01-15 22:38:42 +03:00