u-boot/arch/arm/mach-rockchip/rk3036/save_boot_param.S
huang lin be1d5e0388 rockchip: rk3036: Add core Soc start-up code
rk3036 only 4K size SRAM for SPL, so only support
timer, uart, sdram driver in SPL stage, when finish
initial sdram, back to bootrom.And in rk3036 sdmmc and
debug uart use same iomux, so if you want to boot from
sdmmc, you must disable debug uart.

Signed-off-by: Lin Huang <hl@rock-chips.com>
Acked-by: Simon Glass <sjg@chromium.org>
Fixed build error for chromebook_jerry, firefly-rk3288:
Signed-off-by: Simon Glass <sjg@chromium.org>

Series-changes: 8
- Fix build error for chromebook_jerry, firefly-rk3288
2015-12-01 08:07:22 -07:00

32 lines
507 B
ArmAsm

/*
* (C) Copyright 2015 Google, Inc
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <linux/linkage.h>
.globl SAVE_SP_ADDR
SAVE_SP_ADDR:
.word 0
/*
* void save_boot_params
*
* Save sp, lr, r1~r12
*/
ENTRY(save_boot_params)
push {r1-r12, lr}
ldr r0, =SAVE_SP_ADDR
str sp, [r0]
b save_boot_params_ret @ back to my caller
ENDPROC(save_boot_params)
.globl back_to_bootrom
ENTRY(back_to_bootrom)
ldr r0, =SAVE_SP_ADDR
ldr sp, [r0]
mov r0, #0
pop {r1-r12, pc}
ENDPROC(back_to_bootrom)