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d1998a9fde
This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
371 lines
12 KiB
C
371 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 STMicroelectronics - All Rights Reserved
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* Author(s): Yannick Fertre <yannick.fertre@st.com> for STMicroelectronics.
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* Philippe Cornu <philippe.cornu@st.com> for STMicroelectronics.
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*
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* This otm8009a panel driver is inspired from the Linux Kernel driver
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* drivers/gpu/drm/panel/panel-orisetech-otm8009a.c.
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*/
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#include <common.h>
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#include <backlight.h>
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#include <dm.h>
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#include <mipi_dsi.h>
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#include <panel.h>
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#include <asm/gpio.h>
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#include <dm/device_compat.h>
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#include <linux/delay.h>
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#include <power/regulator.h>
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#define OTM8009A_BACKLIGHT_DEFAULT 240
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#define OTM8009A_BACKLIGHT_MAX 255
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/* Manufacturer Command Set */
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#define MCS_ADRSFT 0x0000 /* Address Shift Function */
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#define MCS_PANSET 0xB3A6 /* Panel Type Setting */
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#define MCS_SD_CTRL 0xC0A2 /* Source Driver Timing Setting */
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#define MCS_P_DRV_M 0xC0B4 /* Panel Driving Mode */
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#define MCS_OSC_ADJ 0xC181 /* Oscillator Adjustment for Idle/Normal mode */
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#define MCS_RGB_VID_SET 0xC1A1 /* RGB Video Mode Setting */
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#define MCS_SD_PCH_CTRL 0xC480 /* Source Driver Precharge Control */
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#define MCS_NO_DOC1 0xC48A /* Command not documented */
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#define MCS_PWR_CTRL1 0xC580 /* Power Control Setting 1 */
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#define MCS_PWR_CTRL2 0xC590 /* Power Control Setting 2 for Normal Mode */
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#define MCS_PWR_CTRL4 0xC5B0 /* Power Control Setting 4 for DC Voltage */
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#define MCS_PANCTRLSET1 0xCB80 /* Panel Control Setting 1 */
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#define MCS_PANCTRLSET2 0xCB90 /* Panel Control Setting 2 */
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#define MCS_PANCTRLSET3 0xCBA0 /* Panel Control Setting 3 */
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#define MCS_PANCTRLSET4 0xCBB0 /* Panel Control Setting 4 */
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#define MCS_PANCTRLSET5 0xCBC0 /* Panel Control Setting 5 */
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#define MCS_PANCTRLSET6 0xCBD0 /* Panel Control Setting 6 */
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#define MCS_PANCTRLSET7 0xCBE0 /* Panel Control Setting 7 */
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#define MCS_PANCTRLSET8 0xCBF0 /* Panel Control Setting 8 */
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#define MCS_PANU2D1 0xCC80 /* Panel U2D Setting 1 */
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#define MCS_PANU2D2 0xCC90 /* Panel U2D Setting 2 */
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#define MCS_PANU2D3 0xCCA0 /* Panel U2D Setting 3 */
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#define MCS_PAND2U1 0xCCB0 /* Panel D2U Setting 1 */
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#define MCS_PAND2U2 0xCCC0 /* Panel D2U Setting 2 */
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#define MCS_PAND2U3 0xCCD0 /* Panel D2U Setting 3 */
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#define MCS_GOAVST 0xCE80 /* GOA VST Setting */
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#define MCS_GOACLKA1 0xCEA0 /* GOA CLKA1 Setting */
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#define MCS_GOACLKA3 0xCEB0 /* GOA CLKA3 Setting */
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#define MCS_GOAECLK 0xCFC0 /* GOA ECLK Setting */
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#define MCS_NO_DOC2 0xCFD0 /* Command not documented */
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#define MCS_GVDDSET 0xD800 /* GVDD/NGVDD */
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#define MCS_VCOMDC 0xD900 /* VCOM Voltage Setting */
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#define MCS_GMCT2_2P 0xE100 /* Gamma Correction 2.2+ Setting */
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#define MCS_GMCT2_2N 0xE200 /* Gamma Correction 2.2- Setting */
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#define MCS_NO_DOC3 0xF5B6 /* Command not documented */
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#define MCS_CMD2_ENA1 0xFF00 /* Enable Access Command2 "CMD2" */
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#define MCS_CMD2_ENA2 0xFF80 /* Enable Access Orise Command2 */
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struct otm8009a_panel_priv {
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struct udevice *reg;
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struct gpio_desc reset;
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};
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static const struct display_timing default_timing = {
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.pixelclock.typ = 29700000,
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.hactive.typ = 480,
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.hfront_porch.typ = 98,
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.hback_porch.typ = 98,
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.hsync_len.typ = 32,
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.vactive.typ = 800,
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.vfront_porch.typ = 15,
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.vback_porch.typ = 14,
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.vsync_len.typ = 10,
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};
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static void otm8009a_dcs_write_buf(struct udevice *dev, const void *data,
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size_t len)
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{
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struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
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struct mipi_dsi_device *device = plat->device;
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if (mipi_dsi_dcs_write_buffer(device, data, len) < 0)
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dev_err(dev, "mipi dsi dcs write buffer failed\n");
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}
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static void otm8009a_dcs_write_buf_hs(struct udevice *dev, const void *data,
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size_t len)
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{
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struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
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struct mipi_dsi_device *device = plat->device;
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/* data will be sent in dsi hs mode (ie. no lpm) */
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device->mode_flags &= ~MIPI_DSI_MODE_LPM;
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if (mipi_dsi_dcs_write_buffer(device, data, len) < 0)
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dev_err(dev, "mipi dsi dcs write buffer failed\n");
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/* restore back the dsi lpm mode */
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device->mode_flags |= MIPI_DSI_MODE_LPM;
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}
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#define dcs_write_seq(dev, seq...) \
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({ \
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static const u8 d[] = { seq }; \
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otm8009a_dcs_write_buf(dev, d, ARRAY_SIZE(d)); \
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})
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#define dcs_write_seq_hs(dev, seq...) \
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({ \
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static const u8 d[] = { seq }; \
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otm8009a_dcs_write_buf_hs(dev, d, ARRAY_SIZE(d)); \
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})
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#define dcs_write_cmd_at(dev, cmd, seq...) \
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({ \
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static const u16 c = cmd; \
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struct udevice *device = dev; \
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dcs_write_seq(device, MCS_ADRSFT, (c) & 0xFF); \
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dcs_write_seq(device, (c) >> 8, seq); \
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})
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static int otm8009a_init_sequence(struct udevice *dev)
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{
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struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
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struct mipi_dsi_device *device = plat->device;
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int ret;
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/* Enter CMD2 */
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dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0x80, 0x09, 0x01);
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/* Enter Orise Command2 */
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dcs_write_cmd_at(dev, MCS_CMD2_ENA2, 0x80, 0x09);
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dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL, 0x30);
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mdelay(10);
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dcs_write_cmd_at(dev, MCS_NO_DOC1, 0x40);
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mdelay(10);
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dcs_write_cmd_at(dev, MCS_PWR_CTRL4 + 1, 0xA9);
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dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 1, 0x34);
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dcs_write_cmd_at(dev, MCS_P_DRV_M, 0x50);
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dcs_write_cmd_at(dev, MCS_VCOMDC, 0x4E);
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dcs_write_cmd_at(dev, MCS_OSC_ADJ, 0x66); /* 65Hz */
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dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 2, 0x01);
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dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 5, 0x34);
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dcs_write_cmd_at(dev, MCS_PWR_CTRL2 + 4, 0x33);
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dcs_write_cmd_at(dev, MCS_GVDDSET, 0x79, 0x79);
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dcs_write_cmd_at(dev, MCS_SD_CTRL + 1, 0x1B);
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dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 2, 0x83);
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dcs_write_cmd_at(dev, MCS_SD_PCH_CTRL + 1, 0x83);
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dcs_write_cmd_at(dev, MCS_RGB_VID_SET, 0x0E);
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dcs_write_cmd_at(dev, MCS_PANSET, 0x00, 0x01);
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dcs_write_cmd_at(dev, MCS_GOAVST, 0x85, 0x01, 0x00, 0x84, 0x01, 0x00);
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dcs_write_cmd_at(dev, MCS_GOACLKA1, 0x18, 0x04, 0x03, 0x39, 0x00, 0x00,
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0x00, 0x18, 0x03, 0x03, 0x3A, 0x00, 0x00, 0x00);
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dcs_write_cmd_at(dev, MCS_GOACLKA3, 0x18, 0x02, 0x03, 0x3B, 0x00, 0x00,
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0x00, 0x18, 0x01, 0x03, 0x3C, 0x00, 0x00, 0x00);
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dcs_write_cmd_at(dev, MCS_GOAECLK, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00,
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0x01, 0x02, 0x00, 0x00);
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dcs_write_cmd_at(dev, MCS_NO_DOC2, 0x00);
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dcs_write_cmd_at(dev, MCS_PANCTRLSET1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
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dcs_write_cmd_at(dev, MCS_PANCTRLSET2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0);
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dcs_write_cmd_at(dev, MCS_PANCTRLSET3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0);
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dcs_write_cmd_at(dev, MCS_PANCTRLSET4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
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dcs_write_cmd_at(dev, MCS_PANCTRLSET5, 0, 4, 4, 4, 4, 4, 0, 0, 0, 0,
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0, 0, 0, 0, 0);
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dcs_write_cmd_at(dev, MCS_PANCTRLSET6, 0, 0, 0, 0, 0, 0, 4, 4, 4, 4,
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4, 0, 0, 0, 0);
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dcs_write_cmd_at(dev, MCS_PANCTRLSET7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0);
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dcs_write_cmd_at(dev, MCS_PANCTRLSET8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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0xFF, 0xFF, 0xFF, 0xFF, 0xFF);
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dcs_write_cmd_at(dev, MCS_PANU2D1, 0x00, 0x26, 0x09, 0x0B, 0x01, 0x25,
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0x00, 0x00, 0x00, 0x00);
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dcs_write_cmd_at(dev, MCS_PANU2D2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x26, 0x0A, 0x0C, 0x02);
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dcs_write_cmd_at(dev, MCS_PANU2D3, 0x25, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
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dcs_write_cmd_at(dev, MCS_PAND2U1, 0x00, 0x25, 0x0C, 0x0A, 0x02, 0x26,
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0x00, 0x00, 0x00, 0x00);
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dcs_write_cmd_at(dev, MCS_PAND2U2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x25, 0x0B, 0x09, 0x01);
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dcs_write_cmd_at(dev, MCS_PAND2U3, 0x26, 0x00, 0x00, 0x00, 0x00, 0x00,
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
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dcs_write_cmd_at(dev, MCS_PWR_CTRL1 + 1, 0x66);
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dcs_write_cmd_at(dev, MCS_NO_DOC3, 0x06);
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dcs_write_cmd_at(dev, MCS_GMCT2_2P, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
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0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
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0x01);
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dcs_write_cmd_at(dev, MCS_GMCT2_2N, 0x00, 0x09, 0x0F, 0x0E, 0x07, 0x10,
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0x0B, 0x0A, 0x04, 0x07, 0x0B, 0x08, 0x0F, 0x10, 0x0A,
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0x01);
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/* Exit CMD2 */
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dcs_write_cmd_at(dev, MCS_CMD2_ENA1, 0xFF, 0xFF, 0xFF);
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ret = mipi_dsi_dcs_nop(device);
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if (ret)
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return ret;
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ret = mipi_dsi_dcs_exit_sleep_mode(device);
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if (ret)
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return ret;
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/* Wait for sleep out exit */
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mdelay(120);
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/* Default portrait 480x800 rgb24 */
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dcs_write_seq(dev, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
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ret = mipi_dsi_dcs_set_column_address(device, 0,
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default_timing.hactive.typ - 1);
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if (ret)
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return ret;
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ret = mipi_dsi_dcs_set_page_address(device, 0,
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default_timing.vactive.typ - 1);
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if (ret)
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return ret;
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/* See otm8009a driver documentation for pixel format descriptions */
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ret = mipi_dsi_dcs_set_pixel_format(device, MIPI_DCS_PIXEL_FMT_24BIT |
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MIPI_DCS_PIXEL_FMT_24BIT << 4);
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if (ret)
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return ret;
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/* Disable CABC feature */
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dcs_write_seq(dev, MIPI_DCS_WRITE_POWER_SAVE, 0x00);
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ret = mipi_dsi_dcs_set_display_on(device);
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if (ret)
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return ret;
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ret = mipi_dsi_dcs_nop(device);
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if (ret)
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return ret;
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/* Send Command GRAM memory write (no parameters) */
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dcs_write_seq(dev, MIPI_DCS_WRITE_MEMORY_START);
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return 0;
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}
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static int otm8009a_panel_enable_backlight(struct udevice *dev)
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{
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struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
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struct mipi_dsi_device *device = plat->device;
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int ret;
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ret = mipi_dsi_attach(device);
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if (ret < 0)
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return ret;
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ret = otm8009a_init_sequence(dev);
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if (ret)
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return ret;
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/*
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* Power on the backlight with the requested brightness
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* Note We can not use mipi_dsi_dcs_set_display_brightness()
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* as otm8009a driver support only 8-bit brightness (1 param).
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*/
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dcs_write_seq(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS,
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OTM8009A_BACKLIGHT_DEFAULT);
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/* Update Brightness Control & Backlight */
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dcs_write_seq(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY, 0x24);
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/* Update Brightness Control & Backlight */
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dcs_write_seq_hs(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY);
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/* Need to wait a few time before sending the first image */
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mdelay(10);
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return 0;
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}
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static int otm8009a_panel_get_display_timing(struct udevice *dev,
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struct display_timing *timings)
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{
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memcpy(timings, &default_timing, sizeof(*timings));
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return 0;
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}
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static int otm8009a_panel_of_to_plat(struct udevice *dev)
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{
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struct otm8009a_panel_priv *priv = dev_get_priv(dev);
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int ret;
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if (IS_ENABLED(CONFIG_DM_REGULATOR)) {
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ret = device_get_supply_regulator(dev, "power-supply",
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&priv->reg);
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if (ret && ret != -ENOENT) {
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dev_err(dev, "Warning: cannot get power supply\n");
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return ret;
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}
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}
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ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->reset,
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GPIOD_IS_OUT);
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if (ret) {
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dev_err(dev, "warning: cannot get reset GPIO\n");
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if (ret != -ENOENT)
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return ret;
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}
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return 0;
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}
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static int otm8009a_panel_probe(struct udevice *dev)
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{
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struct otm8009a_panel_priv *priv = dev_get_priv(dev);
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struct mipi_dsi_panel_plat *plat = dev_get_plat(dev);
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int ret;
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if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
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dev_dbg(dev, "enable regulator '%s'\n", priv->reg->name);
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ret = regulator_set_enable(priv->reg, true);
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if (ret)
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return ret;
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}
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/* reset panel */
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dm_gpio_set_value(&priv->reset, true);
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mdelay(1); /* >50us */
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dm_gpio_set_value(&priv->reset, false);
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mdelay(10); /* >5ms */
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/* fill characteristics of DSI data link */
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plat->lanes = 2;
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plat->format = MIPI_DSI_FMT_RGB888;
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plat->mode_flags = MIPI_DSI_MODE_VIDEO |
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MIPI_DSI_MODE_VIDEO_BURST |
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MIPI_DSI_MODE_LPM;
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return 0;
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}
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static const struct panel_ops otm8009a_panel_ops = {
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.enable_backlight = otm8009a_panel_enable_backlight,
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.get_display_timing = otm8009a_panel_get_display_timing,
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};
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static const struct udevice_id otm8009a_panel_ids[] = {
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{ .compatible = "orisetech,otm8009a" },
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{ }
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};
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U_BOOT_DRIVER(otm8009a_panel) = {
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.name = "otm8009a_panel",
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.id = UCLASS_PANEL,
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.of_match = otm8009a_panel_ids,
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.ops = &otm8009a_panel_ops,
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.of_to_plat = otm8009a_panel_of_to_plat,
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.probe = otm8009a_panel_probe,
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.plat_auto = sizeof(struct mipi_dsi_panel_plat),
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.priv_auto = sizeof(struct otm8009a_panel_priv),
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};
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