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532de8d99c
mt7531 is a 7-ports switch with 5 embedded giga phys, and uses the same
MAC design of mt7530. The cpu port6 supports SGMII only. The cpu port5
supports RGMII or SGMII in different model.
mt7531 is connected to mt7622 via both RGMII and SGMII interfaces.
In this patch, mt7531 cpu port5 or port6 is configured to maximum
capability to align CPU MAC setting.
The dts has been committed in the commit 6efa450565 ("arm: dts:
mediatek: add ethernet and sgmii dts node for mt7622")
Signed-off-by: Landen Chao <landen.chao@mediatek.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
413 lines
11 KiB
C
413 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2018 MediaTek Inc.
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*
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* Author: Weijie Gao <weijie.gao@mediatek.com>
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* Author: Mark Lee <mark-mc.lee@mediatek.com>
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*/
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#ifndef _MTK_ETH_H_
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#define _MTK_ETH_H_
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/* Frame Engine Register Bases */
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#define PDMA_BASE 0x0800
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#define GDMA1_BASE 0x0500
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#define GDMA2_BASE 0x1500
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#define GMAC_BASE 0x10000
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/* Ethernet subsystem registers */
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#define ETHSYS_SYSCFG0_REG 0x14
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#define SYSCFG0_GE_MODE_S(n) (12 + ((n) * 2))
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#define SYSCFG0_GE_MODE_M 0x3
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#define SYSCFG0_SGMII_SEL_M (0x3 << 8)
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#define SYSCFG0_SGMII_SEL(gmac) ((!(gmac)) ? BIT(9) : BIT(8))
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#define ETHSYS_CLKCFG0_REG 0x2c
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#define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
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/* SYSCFG0_GE_MODE: GE Modes */
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#define GE_MODE_RGMII 0
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#define GE_MODE_MII 1
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#define GE_MODE_MII_PHY 2
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#define GE_MODE_RMII 3
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/* SGMII subsystem config registers */
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#define SGMSYS_PCS_CONTROL_1 0x0
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#define SGMII_LINK_STATUS BIT(18)
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#define SGMII_AN_ENABLE BIT(12)
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#define SGMII_AN_RESTART BIT(9)
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#define SGMSYS_SGMII_MODE 0x20
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#define SGMII_FORCE_MODE 0x31120019
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#define SGMSYS_QPHY_PWR_STATE_CTRL 0xe8
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#define SGMII_PHYA_PWD BIT(4)
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#define SGMSYS_GEN2_SPEED 0x2028
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#define SGMSYS_SPEED_2500 BIT(2)
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/* Frame Engine Registers */
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/* PDMA */
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#define TX_BASE_PTR_REG(n) (0x000 + (n) * 0x10)
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#define TX_MAX_CNT_REG(n) (0x004 + (n) * 0x10)
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#define TX_CTX_IDX_REG(n) (0x008 + (n) * 0x10)
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#define TX_DTX_IDX_REG(n) (0x00c + (n) * 0x10)
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#define RX_BASE_PTR_REG(n) (0x100 + (n) * 0x10)
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#define RX_MAX_CNT_REG(n) (0x104 + (n) * 0x10)
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#define RX_CRX_IDX_REG(n) (0x108 + (n) * 0x10)
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#define RX_DRX_IDX_REG(n) (0x10c + (n) * 0x10)
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#define PDMA_GLO_CFG_REG 0x204
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#define TX_WB_DDONE BIT(6)
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#define RX_DMA_BUSY BIT(3)
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#define RX_DMA_EN BIT(2)
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#define TX_DMA_BUSY BIT(1)
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#define TX_DMA_EN BIT(0)
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#define PDMA_RST_IDX_REG 0x208
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#define RST_DRX_IDX0 BIT(16)
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#define RST_DTX_IDX0 BIT(0)
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/* GDMA */
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#define GDMA_IG_CTRL_REG 0x000
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#define GDM_ICS_EN BIT(22)
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#define GDM_TCS_EN BIT(21)
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#define GDM_UCS_EN BIT(20)
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#define STRP_CRC BIT(16)
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#define MYMAC_DP_S 12
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#define MYMAC_DP_M 0xf000
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#define BC_DP_S 8
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#define BC_DP_M 0xf00
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#define MC_DP_S 4
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#define MC_DP_M 0xf0
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#define UN_DP_S 0
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#define UN_DP_M 0x0f
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#define GDMA_MAC_LSB_REG 0x008
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#define GDMA_MAC_MSB_REG 0x00c
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/* MYMAC_DP/BC_DP/MC_DP/UN_DP: Destination ports */
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#define DP_PDMA 0
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#define DP_GDMA1 1
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#define DP_GDMA2 2
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#define DP_PPE 4
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#define DP_QDMA 5
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#define DP_DISCARD 7
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/* GMAC Registers */
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#define GMAC_PIAC_REG 0x0004
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#define PHY_ACS_ST BIT(31)
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#define MDIO_REG_ADDR_S 25
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#define MDIO_REG_ADDR_M 0x3e000000
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#define MDIO_PHY_ADDR_S 20
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#define MDIO_PHY_ADDR_M 0x1f00000
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#define MDIO_CMD_S 18
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#define MDIO_CMD_M 0xc0000
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#define MDIO_ST_S 16
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#define MDIO_ST_M 0x30000
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#define MDIO_RW_DATA_S 0
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#define MDIO_RW_DATA_M 0xffff
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/* MDIO_CMD: MDIO commands */
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#define MDIO_CMD_ADDR 0
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#define MDIO_CMD_WRITE 1
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#define MDIO_CMD_READ 2
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#define MDIO_CMD_READ_C45 3
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/* MDIO_ST: MDIO start field */
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#define MDIO_ST_C45 0
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#define MDIO_ST_C22 1
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#define GMAC_PORT_MCR(p) (0x0100 + (p) * 0x100)
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#define MAC_RX_PKT_LEN_S 24
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#define MAC_RX_PKT_LEN_M 0x3000000
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#define IPG_CFG_S 18
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#define IPG_CFG_M 0xc0000
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#define MAC_MODE BIT(16)
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#define FORCE_MODE BIT(15)
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#define MAC_TX_EN BIT(14)
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#define MAC_RX_EN BIT(13)
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#define BKOFF_EN BIT(9)
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#define BACKPR_EN BIT(8)
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#define FORCE_RX_FC BIT(5)
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#define FORCE_TX_FC BIT(4)
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#define FORCE_SPD_S 2
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#define FORCE_SPD_M 0x0c
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#define FORCE_DPX BIT(1)
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#define FORCE_LINK BIT(0)
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/* Values of IPG_CFG */
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#define IPG_96BIT 0
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#define IPG_96BIT_WITH_SHORT_IPG 1
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#define IPG_64BIT 2
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/* MAC_RX_PKT_LEN: Max RX packet length */
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#define MAC_RX_PKT_LEN_1518 0
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#define MAC_RX_PKT_LEN_1536 1
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#define MAC_RX_PKT_LEN_1552 2
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#define MAC_RX_PKT_LEN_JUMBO 3
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/* FORCE_SPD: Forced link speed */
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#define SPEED_10M 0
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#define SPEED_100M 1
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#define SPEED_1000M 2
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#define GMAC_TRGMII_RCK_CTRL 0x300
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#define RX_RST BIT(31)
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#define RXC_DQSISEL BIT(30)
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#define GMAC_TRGMII_TD_ODT(n) (0x354 + (n) * 8)
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#define TD_DM_DRVN_S 4
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#define TD_DM_DRVN_M 0xf0
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#define TD_DM_DRVP_S 0
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#define TD_DM_DRVP_M 0x0f
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/* MT7530 Registers */
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#define PCR_REG(p) (0x2004 + (p) * 0x100)
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#define PORT_MATRIX_S 16
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#define PORT_MATRIX_M 0xff0000
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#define PVC_REG(p) (0x2010 + (p) * 0x100)
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#define STAG_VPID_S 16
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#define STAG_VPID_M 0xffff0000
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#define VLAN_ATTR_S 6
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#define VLAN_ATTR_M 0xc0
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/* VLAN_ATTR: VLAN attributes */
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#define VLAN_ATTR_USER 0
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#define VLAN_ATTR_STACK 1
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#define VLAN_ATTR_TRANSLATION 2
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#define VLAN_ATTR_TRANSPARENT 3
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#define PMCR_REG(p) (0x3000 + (p) * 0x100)
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/* XXX: all fields of MT7530 are defined under GMAC_PORT_MCR
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* MT7531 specific fields are defined below
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*/
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#define FORCE_MODE_EEE1G BIT(25)
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#define FORCE_MODE_EEE100 BIT(26)
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#define FORCE_MODE_TX_FC BIT(27)
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#define FORCE_MODE_RX_FC BIT(28)
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#define FORCE_MODE_DPX BIT(29)
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#define FORCE_MODE_SPD BIT(30)
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#define FORCE_MODE_LNK BIT(31)
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#define MT7531_FORCE_MODE FORCE_MODE_EEE1G | FORCE_MODE_EEE100 |\
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FORCE_MODE_TX_FC | FORCE_MODE_RX_FC | \
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FORCE_MODE_DPX | FORCE_MODE_SPD | \
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FORCE_MODE_LNK
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/* MT7531 SGMII Registers */
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#define MT7531_SGMII_REG_BASE 0x5000
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#define MT7531_SGMII_REG_PORT_BASE 0x1000
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#define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
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(p) * MT7531_SGMII_REG_PORT_BASE + (r))
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#define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(((p) - 5), 0x00)
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#define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(((p) - 5), 0x20)
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#define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(((p) - 5), 0xe8)
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#define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(((p) - 5), 0x128)
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/* XXX: all fields of MT7531 SGMII are defined under SGMSYS */
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/* MT753x System Control Register */
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#define SYS_CTRL_REG 0x7000
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#define SW_PHY_RST BIT(2)
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#define SW_SYS_RST BIT(1)
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#define SW_REG_RST BIT(0)
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/* MT7531 */
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#define MT7531_PHY_IAC 0x701c
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/* XXX: all fields are defined under GMAC_PIAC_REG */
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#define MT7531_CLKGEN_CTRL 0x7500
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#define CLK_SKEW_OUT_S 8
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#define CLK_SKEW_OUT_M 0x300
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#define CLK_SKEW_IN_S 6
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#define CLK_SKEW_IN_M 0xc0
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#define RXCLK_NO_DELAY BIT(5)
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#define TXCLK_NO_REVERSE BIT(4)
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#define GP_MODE_S 1
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#define GP_MODE_M 0x06
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#define GP_CLK_EN BIT(0)
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/* Values of GP_MODE */
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#define GP_MODE_RGMII 0
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#define GP_MODE_MII 1
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#define GP_MODE_REV_MII 2
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/* Values of CLK_SKEW_IN */
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#define CLK_SKEW_IN_NO_CHANGE 0
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#define CLK_SKEW_IN_DELAY_100PPS 1
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#define CLK_SKEW_IN_DELAY_200PPS 2
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#define CLK_SKEW_IN_REVERSE 3
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/* Values of CLK_SKEW_OUT */
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#define CLK_SKEW_OUT_NO_CHANGE 0
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#define CLK_SKEW_OUT_DELAY_100PPS 1
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#define CLK_SKEW_OUT_DELAY_200PPS 2
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#define CLK_SKEW_OUT_REVERSE 3
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#define HWTRAP_REG 0x7800
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/* MT7530 Modified Hardware Trap Status Registers */
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#define MHWTRAP_REG 0x7804
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#define CHG_TRAP BIT(16)
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#define LOOPDET_DIS BIT(14)
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#define P5_INTF_SEL_S 13
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#define P5_INTF_SEL_M 0x2000
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#define SMI_ADDR_S 11
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#define SMI_ADDR_M 0x1800
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#define XTAL_FSEL_S 9
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#define XTAL_FSEL_M 0x600
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#define P6_INTF_DIS BIT(8)
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#define P5_INTF_MODE_S 7
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#define P5_INTF_MODE_M 0x80
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#define P5_INTF_DIS BIT(6)
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#define C_MDIO_BPS BIT(5)
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#define CHIP_MODE_S 0
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#define CHIP_MODE_M 0x0f
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/* P5_INTF_SEL: Interface type of Port5 */
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#define P5_INTF_SEL_GPHY 0
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#define P5_INTF_SEL_GMAC5 1
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/* P5_INTF_MODE: Interface mode of Port5 */
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#define P5_INTF_MODE_GMII_MII 0
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#define P5_INTF_MODE_RGMII 1
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#define MT7530_P6ECR 0x7830
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#define P6_INTF_MODE_M 0x3
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#define P6_INTF_MODE_S 0
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/* P6_INTF_MODE: Interface mode of Port6 */
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#define P6_INTF_MODE_RGMII 0
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#define P6_INTF_MODE_TRGMII 1
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#define NUM_TRGMII_CTRL 5
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#define MT7530_TRGMII_RD(n) (0x7a10 + (n) * 8)
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#define RD_TAP_S 0
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#define RD_TAP_M 0x7f
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#define MT7530_TRGMII_TD_ODT(n) (0x7a54 + (n) * 8)
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/* XXX: all fields are defined under GMAC_TRGMII_TD_ODT */
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/* TOP Signals Status Register */
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#define MT7531_TOP_SIG_SR 0x780c
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#define PAD_MCM_SMI_EN BIT(0)
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#define PAD_DUAL_SGMII_EN BIT(1)
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/* MT7531 PLLGP Registers */
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#define MT7531_PLLGP_EN 0x7820
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#define EN_COREPLL BIT(2)
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#define SW_CLKSW BIT(1)
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#define SW_PLLGP BIT(0)
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#define MT7531_PLLGP_CR0 0x78a8
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#define RG_COREPLL_EN BIT(22)
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#define RG_COREPLL_POSDIV_S 23
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#define RG_COREPLL_POSDIV_M 0x3800000
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#define RG_COREPLL_SDM_PCW_S 1
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#define RG_COREPLL_SDM_PCW_M 0x3ffffe
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#define RG_COREPLL_SDM_PCW_CHG BIT(0)
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/* MT7531 RGMII and SGMII PLL clock */
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#define MT7531_ANA_PLLGP_CR2 0x78b0
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#define MT7531_ANA_PLLGP_CR5 0x78bc
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/* MT7531 GPIO GROUP IOLB SMT0 Control */
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#define MT7531_SMT0_IOLB 0x7f04
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#define SMT_IOLB_5_SMI_MDC_EN BIT(5)
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/* MT7530 GPHY MDIO Indirect Access Registers */
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#define MII_MMD_ACC_CTL_REG 0x0d
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#define MMD_CMD_S 14
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#define MMD_CMD_M 0xc000
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#define MMD_DEVAD_S 0
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#define MMD_DEVAD_M 0x1f
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/* MMD_CMD: MMD commands */
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#define MMD_ADDR 0
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#define MMD_DATA 1
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#define MMD_DATA_RW_POST_INC 2
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#define MMD_DATA_W_POST_INC 3
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#define MII_MMD_ADDR_DATA_REG 0x0e
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/* MT7530 GPHY MDIO MMD Registers */
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#define CORE_PLL_GROUP2 0x401
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#define RG_SYSPLL_EN_NORMAL BIT(15)
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#define RG_SYSPLL_VODEN BIT(14)
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#define RG_SYSPLL_POSDIV_S 5
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#define RG_SYSPLL_POSDIV_M 0x60
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#define CORE_PLL_GROUP4 0x403
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#define MT7531_BYPASS_MODE BIT(4)
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#define MT7531_POWER_ON_OFF BIT(5)
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#define RG_SYSPLL_DDSFBK_EN BIT(12)
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#define RG_SYSPLL_BIAS_EN BIT(11)
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#define RG_SYSPLL_BIAS_LPF_EN BIT(10)
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#define CORE_PLL_GROUP5 0x404
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#define RG_LCDDS_PCW_NCPO1_S 0
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#define RG_LCDDS_PCW_NCPO1_M 0xffff
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#define CORE_PLL_GROUP6 0x405
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#define RG_LCDDS_PCW_NCPO0_S 0
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#define RG_LCDDS_PCW_NCPO0_M 0xffff
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#define CORE_PLL_GROUP7 0x406
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#define RG_LCDDS_PWDB BIT(15)
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#define RG_LCDDS_ISO_EN BIT(13)
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#define RG_LCCDS_C_S 4
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#define RG_LCCDS_C_M 0x70
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#define RG_LCDDS_PCW_NCPO_CHG BIT(3)
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#define CORE_PLL_GROUP10 0x409
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#define RG_LCDDS_SSC_DELTA_S 0
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#define RG_LCDDS_SSC_DELTA_M 0xfff
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#define CORE_PLL_GROUP11 0x40a
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#define RG_LCDDS_SSC_DELTA1_S 0
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#define RG_LCDDS_SSC_DELTA1_M 0xfff
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#define CORE_GSWPLL_GRP1 0x40d
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#define RG_GSWPLL_POSDIV_200M_S 12
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#define RG_GSWPLL_POSDIV_200M_M 0x3000
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#define RG_GSWPLL_EN_PRE BIT(11)
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#define RG_GSWPLL_FBKDIV_200M_S 0
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#define RG_GSWPLL_FBKDIV_200M_M 0xff
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#define CORE_GSWPLL_GRP2 0x40e
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#define RG_GSWPLL_POSDIV_500M_S 8
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#define RG_GSWPLL_POSDIV_500M_M 0x300
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#define RG_GSWPLL_FBKDIV_500M_S 0
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#define RG_GSWPLL_FBKDIV_500M_M 0xff
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#define CORE_TRGMII_GSW_CLK_CG 0x410
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#define REG_GSWCK_EN BIT(0)
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#define REG_TRGMIICK_EN BIT(1)
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/* Extend PHY Control Register 3 */
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#define PHY_EXT_REG_14 0x14
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/* Fields of PHY_EXT_REG_14 */
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#define PHY_EN_DOWN_SHFIT BIT(4)
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/* Extend PHY Control Register 4 */
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#define PHY_EXT_REG_17 0x17
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/* Fields of PHY_EXT_REG_17 */
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#define PHY_LINKDOWN_POWER_SAVING_EN BIT(4)
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/* PHY RXADC Control Register 7 */
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#define PHY_DEV1E_REG_0C6 0x0c6
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/* Fields of PHY_DEV1E_REG_0C6 */
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#define PHY_POWER_SAVING_S 8
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#define PHY_POWER_SAVING_M 0x300
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#define PHY_POWER_SAVING_TX 0x0
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#endif /* _MTK_ETH_H_ */
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