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3a29afcbbf
Alignment with kernel directory name as it have already bindings for
DDR controllers in the directory:
Documentation/devicetree/bindings/memory-controller
PS: the drivers using RAM u-class should be associated with
this binding directory
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
46 lines
1.6 KiB
Text
46 lines
1.6 KiB
Text
Texas Instruments' K3 AM654 DDRSS
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=================================
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K3 based AM654 devices has DDR memory subsystem that comprises
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Synopys DDR controller, Synopsis DDR phy and wrapper logic to
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integrate these blocks into the device. This DDR subsystem
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provides an interface to external SDRAM devices. This DDRSS driver
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adds support for the initialization of the external SDRAM devices by
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configuring the DDRSS registers and using the buitin PHY
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initialization routines.
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DDRSS device node:
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==================
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Required properties:
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--------------------
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- compatible: Shall be: "ti,am654-ddrss"
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- reg-names ss - Map the sub system wrapper logic region
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ctl - Map the controller region
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phy - Map the PHY region
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- reg: Contains the register map per reg-names.
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- power-domains: Should contain a phandle to a PM domain provider node
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and an args specifier containing the DDRSS device id
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value. This property is as per the binding,
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doc/device-tree-bindings/power/ti,sci-pm-domain.txt
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- clocks: Must contain an entry for enabling DDR clock. Should
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be defined as per the appropriate clock bindings consumer
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usage in doc/device-tree-bindings/clock/ti,sci-clk.txt
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Optional Properties:
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--------------------
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- clock-frequency: Frequency at which DDR pll should be locked.
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If not provided, default frequency will be used.
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Example (AM65x):
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================
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memory-controller: memory-controller@298e000 {
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compatible = "ti,am654-ddrss";
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reg = <0x0298e000 0x200>,
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<0x02980000 0x4000>,
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<0x02988000 0x2000>;
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reg-names = "ss", "ctl", "phy";
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clocks = <&k3_clks 20 0>;
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power-domains = <&k3_pds 20>;
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u-boot,dm-spl;
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};
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