mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
35546f6f20
This adds support for IS1 board. Pretty usual socfpga board, 256MB of RAM, does not have MMC, two SPI chips, one ethernet port, two additional ethernet ports connected to the FPGA. Signed-off-by: Pavel Machek <pavel@denx.de>
85 lines
3.1 KiB
C
85 lines
3.1 KiB
C
/*
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* Altera SoCFPGA Clock and PLL configuration
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __SOCFPGA_PLL_CONFIG_H__
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#define __SOCFPGA_PLL_CONFIG_H__
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#define CONFIG_HPS_DBCTRL_STAYOSC1 1
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#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0
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#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 59
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#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0
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#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0
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#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0
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#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4
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#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511
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#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1
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#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1
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#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0
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#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1
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#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0
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#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1
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#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1
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#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0
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#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39
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#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0
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#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511
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#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3
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#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511
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#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511
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#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4
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#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39
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#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0
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#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4
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#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4
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#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4
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#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249
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#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2
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#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2
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#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1
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#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0
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#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31
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#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0
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#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1
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#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0
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#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0
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#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0
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#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1
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#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4
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#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5
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#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
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#define CONFIG_HPS_CLK_OSC1_HZ 25000000
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#define CONFIG_HPS_CLK_OSC2_HZ 25000000
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#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0
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#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0
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#define CONFIG_HPS_CLK_MAINVCO_HZ 1500000000
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#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000
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#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000
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#define CONFIG_HPS_CLK_EMAC0_HZ 250000000
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#define CONFIG_HPS_CLK_EMAC1_HZ 250000000
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#define CONFIG_HPS_CLK_USBCLK_HZ 200000000
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#define CONFIG_HPS_CLK_NAND_HZ 488281
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#define CONFIG_HPS_CLK_SDMMC_HZ 1953125
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#define CONFIG_HPS_CLK_QSPI_HZ 375000000
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#define CONFIG_HPS_CLK_SPIM_HZ 12500000
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#define CONFIG_HPS_CLK_CAN0_HZ 12500000
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#define CONFIG_HPS_CLK_CAN1_HZ 12500000
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#define CONFIG_HPS_CLK_GPIODB_HZ 32000
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#define CONFIG_HPS_CLK_L4_MP_HZ 100000000
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#define CONFIG_HPS_CLK_L4_SP_HZ 100000000
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#define CONFIG_HPS_ALTERAGRP_MPUCLK 1
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#define CONFIG_HPS_ALTERAGRP_MAINCLK 4
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#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4
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#endif /* __SOCFPGA_PLL_CONFIG_H__ */
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