mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-27 07:01:24 +00:00
1221ce459d
Now, arch/${ARCH}/include/asm/errno.h and include/linux/errno.h have
the same content. (both just wrap <asm-generic/errno.h>)
Replace all include directives for <asm/errno.h> with <linux/errno.h>.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
[trini: Fixup include/clk.]
Signed-off-by: Tom Rini <trini@konsulko.com>
271 lines
6.9 KiB
C
271 lines
6.9 KiB
C
/*
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* Copyright (C) 2013 Gateworks Corporation
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*
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* Author: Tim Harvey <tharvey@gateworks.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/errno.h>
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#include <common.h>
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#include <i2c.h>
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#include <linux/ctype.h>
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#include "ventana_eeprom.h"
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#include "gsc.h"
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/*
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* The Gateworks System Controller will fail to ACK a master transaction if
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* it is busy, which can occur during its 1HZ timer tick while reading ADC's.
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* When this does occur, it will never be busy long enough to fail more than
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* 2 back-to-back transfers. Thus we wrap i2c_read and i2c_write with
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* 3 retries.
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*/
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int gsc_i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
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{
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int retry = 3;
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int n = 0;
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int ret;
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while (n++ < retry) {
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ret = i2c_read(chip, addr, alen, buf, len);
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if (!ret)
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break;
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debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
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n, ret);
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if (ret != -ENODEV)
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break;
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mdelay(10);
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}
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return ret;
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}
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int gsc_i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
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{
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int retry = 3;
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int n = 0;
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int ret;
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while (n++ < retry) {
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ret = i2c_write(chip, addr, alen, buf, len);
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if (!ret)
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break;
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debug("%s: 0x%02x 0x%02x retry%d: %d\n", __func__, chip, addr,
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n, ret);
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if (ret != -ENODEV)
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break;
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mdelay(10);
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}
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mdelay(100);
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return ret;
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}
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static void read_hwmon(const char *name, uint reg, uint size)
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{
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unsigned char buf[3];
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uint ui;
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printf("%-8s:", name);
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memset(buf, 0, sizeof(buf));
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if (gsc_i2c_read(GSC_HWMON_ADDR, reg, 1, buf, size)) {
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puts("fRD\n");
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} else {
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ui = buf[0] | (buf[1]<<8) | (buf[2]<<16);
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if (reg == GSC_HWMON_TEMP && ui > 0x8000)
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ui -= 0xffff;
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if (ui == 0xffffff)
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puts("invalid\n");
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else
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printf("%d\n", ui);
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}
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}
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int gsc_info(int verbose)
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{
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unsigned char buf[16];
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i2c_set_bus_num(0);
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if (gsc_i2c_read(GSC_SC_ADDR, 0, 1, buf, 16))
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return CMD_RET_FAILURE;
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printf("GSC: v%d", buf[GSC_SC_FWVER]);
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printf(" 0x%04x", buf[GSC_SC_FWCRC] | buf[GSC_SC_FWCRC+1]<<8);
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printf(" WDT:%sabled", (buf[GSC_SC_CTRL1] & (1<<GSC_SC_CTRL1_WDEN))
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? "en" : "dis");
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if (buf[GSC_SC_STATUS] & (1 << GSC_SC_IRQ_WATCHDOG)) {
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buf[GSC_SC_STATUS] &= ~(1 << GSC_SC_IRQ_WATCHDOG);
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puts(" WDT_RESET");
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gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1,
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&buf[GSC_SC_STATUS], 1);
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}
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if (!gsc_i2c_read(GSC_HWMON_ADDR, GSC_HWMON_TEMP, 1, buf, 2)) {
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int ui = buf[0] | buf[1]<<8;
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if (ui > 0x8000)
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ui -= 0xffff;
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printf(" board temp at %dC", ui / 10);
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}
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puts("\n");
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if (!verbose)
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return CMD_RET_SUCCESS;
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read_hwmon("Temp", GSC_HWMON_TEMP, 2);
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read_hwmon("VIN", GSC_HWMON_VIN, 3);
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read_hwmon("VBATT", GSC_HWMON_VBATT, 3);
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read_hwmon("VDD_3P3", GSC_HWMON_VDD_3P3, 3);
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read_hwmon("VDD_ARM", GSC_HWMON_VDD_CORE, 3);
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read_hwmon("VDD_SOC", GSC_HWMON_VDD_SOC, 3);
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read_hwmon("VDD_HIGH", GSC_HWMON_VDD_HIGH, 3);
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read_hwmon("VDD_DDR", GSC_HWMON_VDD_DDR, 3);
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read_hwmon("VDD_5P0", GSC_HWMON_VDD_5P0, 3);
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if (strncasecmp((const char*) ventana_info.model, "GW553", 5))
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read_hwmon("VDD_2P5", GSC_HWMON_VDD_2P5, 3);
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read_hwmon("VDD_1P8", GSC_HWMON_VDD_1P8, 3);
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read_hwmon("VDD_IO2", GSC_HWMON_VDD_IO2, 3);
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switch (ventana_info.model[3]) {
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case '1': /* GW51xx */
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read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
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break;
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case '2': /* GW52xx */
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break;
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case '3': /* GW53xx */
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read_hwmon("VDD_IO4", GSC_HWMON_VDD_IO4, 3); /* -C rev */
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read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
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break;
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case '4': /* GW54xx */
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read_hwmon("VDD_IO3", GSC_HWMON_VDD_IO4, 3); /* -C rev */
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read_hwmon("VDD_GPS", GSC_HWMON_VDD_IO3, 3);
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break;
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case '5': /* GW55xx */
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break;
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}
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return 0;
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}
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/*
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* The Gateworks System Controller implements a boot
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* watchdog (always enabled) as a workaround for IMX6 boot related
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* errata such as:
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* ERR005768 - no fix scheduled
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* ERR006282 - fixed in silicon r1.2
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* ERR007117 - fixed in silicon r1.3
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* ERR007220 - fixed in silicon r1.3
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* ERR007926 - no fix scheduled
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* see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
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*
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* Disable the boot watchdog
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*/
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int gsc_boot_wd_disable(void)
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{
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u8 reg;
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i2c_set_bus_num(CONFIG_I2C_GSC);
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if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1)) {
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reg |= (1 << GSC_SC_CTRL1_WDDIS);
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if (!gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
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return 0;
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}
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puts("Error: could not disable GSC Watchdog\n");
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return 1;
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}
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#ifdef CONFIG_CMD_GSC
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static int do_gsc_sleep(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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unsigned char reg;
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unsigned long secs = 0;
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if (argc < 2)
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return CMD_RET_USAGE;
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secs = simple_strtoul(argv[1], NULL, 10);
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printf("GSC Sleeping for %ld seconds\n", secs);
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i2c_set_bus_num(0);
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reg = (secs >> 24) & 0xff;
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if (gsc_i2c_write(GSC_SC_ADDR, 9, 1, ®, 1))
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goto error;
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reg = (secs >> 16) & 0xff;
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if (gsc_i2c_write(GSC_SC_ADDR, 8, 1, ®, 1))
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goto error;
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reg = (secs >> 8) & 0xff;
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if (gsc_i2c_write(GSC_SC_ADDR, 7, 1, ®, 1))
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goto error;
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reg = secs & 0xff;
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if (gsc_i2c_write(GSC_SC_ADDR, 6, 1, ®, 1))
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goto error;
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if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
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goto error;
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reg |= (1 << 2);
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if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
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goto error;
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reg &= ~(1 << 2);
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reg |= 0x3;
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if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
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goto error;
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return CMD_RET_SUCCESS;
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error:
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printf("i2c error\n");
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return CMD_RET_FAILURE;
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}
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static int do_gsc_wd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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unsigned char reg;
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if (argc < 2)
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return CMD_RET_USAGE;
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if (strcasecmp(argv[1], "enable") == 0) {
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int timeout = 0;
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if (argc > 2)
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timeout = simple_strtoul(argv[2], NULL, 10);
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i2c_set_bus_num(0);
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if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
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return CMD_RET_FAILURE;
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reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
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if (timeout == 60)
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reg |= (1 << GSC_SC_CTRL1_WDTIME);
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else
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timeout = 30;
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reg |= (1 << GSC_SC_CTRL1_WDEN);
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if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
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return CMD_RET_FAILURE;
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printf("GSC Watchdog enabled with timeout=%d seconds\n",
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timeout);
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} else if (strcasecmp(argv[1], "disable") == 0) {
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i2c_set_bus_num(0);
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if (gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
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return CMD_RET_FAILURE;
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reg &= ~((1 << GSC_SC_CTRL1_WDEN) | (1 << GSC_SC_CTRL1_WDTIME));
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if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, ®, 1))
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return CMD_RET_FAILURE;
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printf("GSC Watchdog disabled\n");
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} else {
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return CMD_RET_USAGE;
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}
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return CMD_RET_SUCCESS;
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}
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static int do_gsc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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if (argc < 2)
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return gsc_info(1);
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if (strcasecmp(argv[1], "wd") == 0)
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return do_gsc_wd(cmdtp, flag, --argc, ++argv);
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else if (strcasecmp(argv[1], "sleep") == 0)
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return do_gsc_sleep(cmdtp, flag, --argc, ++argv);
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return CMD_RET_USAGE;
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}
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U_BOOT_CMD(
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gsc, 4, 1, do_gsc, "GSC configuration",
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"[wd enable [30|60]]|[wd disable]|[sleep <secs>]\n"
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);
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#endif /* CONFIG_CMD_GSC */
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