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f3dff695e1
Set TXFIFOTHRESH to adjust ddr pipeline delay for successful large usb writes Signed-off-by: Nikhil Badola <nikhil.badola@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com> |
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mpc5xx | ||
mpc5xxx | ||
mpc8xx | ||
mpc8xxx | ||
mpc83xx | ||
mpc85xx | ||
mpc86xx | ||
mpc512x | ||
mpc824x | ||
mpc8260 | ||
ppc4xx | ||
Makefile |