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0fbf31f966
Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
48 lines
1.8 KiB
C
48 lines
1.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
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*/
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#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
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#define _SOCFPGA_SOC64_BASE_HARDWARE_H_
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#define SOCFPGA_CCU_ADDRESS 0xf7000000
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#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
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#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
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#define SOCFPGA_SDR_ADDRESS 0xf8011000
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#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \
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IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
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#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200
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#else
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#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100
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#endif
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#define SOCFPGA_SMMU_ADDRESS 0xfa000000
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#define SOCFPGA_MAILBOX_ADDRESS 0xffa30000
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#define SOCFPGA_UART0_ADDRESS 0xffc02000
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#define SOCFPGA_UART1_ADDRESS 0xffc02100
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#define SOCFPGA_SPTIMER0_ADDRESS 0xffc03000
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#define SOCFPGA_SPTIMER1_ADDRESS 0xffc03100
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#define SOCFPGA_SYSTIMER0_ADDRESS 0xffd00000
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#define SOCFPGA_SYSTIMER1_ADDRESS 0xffd00100
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#define SOCFPGA_L4WD0_ADDRESS 0xffd00200
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#define SOCFPGA_L4WD1_ADDRESS 0xffd00300
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#define SOCFPGA_L4WD2_ADDRESS 0xffd00400
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#define SOCFPGA_L4WD3_ADDRESS 0xffd00500
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#define SOCFPGA_GTIMER_SEC_ADDRESS 0xffd01000
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#define SOCFPGA_GTIMER_NSEC_ADDRESS 0xffd02000
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#define SOCFPGA_CLKMGR_ADDRESS 0xffd10000
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#define SOCFPGA_RSTMGR_ADDRESS 0xffd11000
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#define SOCFPGA_SYSMGR_ADDRESS 0xffd12000
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#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS 0xffd13000
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#define SOCFPGA_FIREWALL_L4_PER 0xffd21000
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#define SOCFPGA_FIREWALL_L4_SYS 0xffd21100
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#define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200
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#define SOCFPGA_FIREWALL_LWSOC2FPGA 0xffd21300
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#define SOCFPGA_FIREWALL_TCU 0xffd21400
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#define SOCFPGA_DMANONSECURE_ADDRESS 0xffda0000
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#define SOCFPGA_DMASECURE_ADDRESS 0xffda1000
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#define SOCFPGA_OCRAM_ADDRESS 0xffe00000
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#define GICD_BASE 0xfffc1000
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#define GICC_BASE 0xfffc2000
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#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
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