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5668c75ce9
Configure PMIC voltages for early stages using updated early i2c write. Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30 Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com>
43 lines
1.1 KiB
C
43 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* (C) Copyright 2010-2013
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* NVIDIA Corporation <www.nvidia.com>
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*
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* (C) Copyright 2021
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* Svyatoslav Ryhel <clamor95@gmail.com>
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*/
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#include <common.h>
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#include <asm/arch-tegra/tegra_i2c.h>
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#include <linux/delay.h>
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/* I2C addr is in 8 bit */
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#define TPS65911_I2C_ADDR 0x5A
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#define TPS65911_VDDCTRL_OP_REG 0x28
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#define TPS65911_VDDCTRL_SR_REG 0x27
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#define TPS65911_VDDCTRL_OP_DATA (0x2400 | TPS65911_VDDCTRL_OP_REG)
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#define TPS65911_VDDCTRL_SR_DATA (0x0100 | TPS65911_VDDCTRL_SR_REG)
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#define TPS62366A_I2C_ADDR 0xC0
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#define TPS62366A_SET1_REG 0x01
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#define TPS62366A_SET1_DATA (0x4600 | TPS62366A_SET1_REG)
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void pmic_enable_cpu_vdd(void)
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{
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/* Set VDD_CORE to 1.200V. */
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tegra_i2c_ll_write(TPS62366A_I2C_ADDR,
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TPS62366A_SET1_DATA);
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udelay(1000);
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/*
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* Bring up CPU VDD via the TPS65911x PMIC on the DVC I2C bus.
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* First set VDD to 1.0125V, then enable the VDD regulator.
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*/
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tegra_i2c_ll_write(TPS65911_I2C_ADDR,
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TPS65911_VDDCTRL_OP_DATA);
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udelay(1000);
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tegra_i2c_ll_write(TPS65911_I2C_ADDR,
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TPS65911_VDDCTRL_SR_DATA);
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udelay(10 * 1000);
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}
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