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ca0973741d
This belongs in the J721e specific file as it is the only place this is used. Any board level users should use the SOC driver. While here, move the J721e and J7200 SoC IDs out of sys_proto.h and into hardware.h. Use a macro borrowed from Rockchip and add the rest of the SoC IDs for completeness and later use. Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
99 lines
2.6 KiB
C
99 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#ifndef _ASM_ARCH_HARDWARE_H_
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#define _ASM_ARCH_HARDWARE_H_
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#include <asm/io.h>
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#ifdef CONFIG_SOC_K3_AM654
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#include "am6_hardware.h"
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#endif
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#ifdef CONFIG_SOC_K3_J721E
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#include "j721e_hardware.h"
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#endif
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#ifdef CONFIG_SOC_K3_J721S2
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#include "j721s2_hardware.h"
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#endif
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#ifdef CONFIG_SOC_K3_AM642
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#include "am64_hardware.h"
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#endif
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#ifdef CONFIG_SOC_K3_AM625
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#include "am62_hardware.h"
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#endif
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#ifdef CONFIG_SOC_K3_AM62A7
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#include "am62a_hardware.h"
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#endif
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/* Assuming these addresses and definitions stay common across K3 devices */
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#define CTRLMMR_WKUP_JTAG_ID (WKUP_CTRL_MMR0_BASE + 0x14)
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#define JTAG_ID_VARIANT_SHIFT 28
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#define JTAG_ID_VARIANT_MASK (0xf << 28)
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#define JTAG_ID_PARTNO_SHIFT 12
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#define JTAG_ID_PARTNO_MASK (0xffff << 12)
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#define JTAG_ID_PARTNO_AM65X 0xbb5a
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#define JTAG_ID_PARTNO_J721E 0xbb64
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#define JTAG_ID_PARTNO_J7200 0xbb6d
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#define JTAG_ID_PARTNO_AM64X 0xbb38
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#define JTAG_ID_PARTNO_J721S2 0xbb75
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#define JTAG_ID_PARTNO_AM62X 0xbb7e
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#define JTAG_ID_PARTNO_AM62AX 0xbb8d
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#define K3_SOC_ID(id, ID) \
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static inline bool soc_is_##id(void) \
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{ \
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u32 soc = (readl(CTRLMMR_WKUP_JTAG_ID) & \
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JTAG_ID_PARTNO_MASK) >> JTAG_ID_PARTNO_SHIFT; \
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return soc == JTAG_ID_PARTNO_##ID; \
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}
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K3_SOC_ID(am65x, AM65X)
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K3_SOC_ID(j721e, J721E)
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K3_SOC_ID(j7200, J7200)
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K3_SOC_ID(am64x, AM64X)
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K3_SOC_ID(j721s2, J721S2)
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K3_SOC_ID(am62x, AM62X)
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K3_SOC_ID(am62ax, AM62AX)
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#define K3_SEC_MGR_SYS_STATUS 0x44234100
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#define SYS_STATUS_DEV_TYPE_SHIFT 0
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#define SYS_STATUS_DEV_TYPE_MASK (0xf)
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#define SYS_STATUS_DEV_TYPE_GP 0x3
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#define SYS_STATUS_DEV_TYPE_TEST 0x5
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#define SYS_STATUS_DEV_TYPE_EMU 0x9
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#define SYS_STATUS_DEV_TYPE_HS 0xa
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#define SYS_STATUS_SUB_TYPE_SHIFT 8
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#define SYS_STATUS_SUB_TYPE_MASK (0xf << 8)
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#define SYS_STATUS_SUB_TYPE_VAL_FS 0xa
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/*
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* The CTRL_MMR0 memory space is divided into several equally-spaced
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* partitions, so defining the partition size allows us to determine
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* register addresses common to those partitions.
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*/
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#define CTRL_MMR0_PARTITION_SIZE 0x4000
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/*
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* CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTRL_MMR0 lock/kick-mechanism
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* shared register definitions. The same registers are also used for
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* PADCFG_MMR lock/kick-mechanism.
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*/
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#define CTRLMMR_LOCK_KICK0 0x1008
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#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
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#define CTRLMMR_LOCK_KICK1 0x100c
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#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
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#define K3_ROM_BOOT_HEADER_MAGIC "EXTBOOT"
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struct rom_extended_boot_data {
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char header[8];
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u32 num_components;
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};
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#endif /* _ASM_ARCH_HARDWARE_H_ */
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