mirror of
https://github.com/AsahiLinux/u-boot
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f35c417c9b
Mov edram_init_banksize() into rk3288.c so that we can re-use the common SPL board file later. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
78 lines
1.7 KiB
C
78 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2016 Rockchip Electronics Co., Ltd
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*/
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#include <asm/armv7.h>
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#include <asm/io.h>
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#include <asm/arch-rockchip/hardware.h>
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#include <asm/arch-rockchip/grf_rk3288.h>
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#include <asm/arch-rockchip/pmu_rk3288.h>
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#include <asm/arch-rockchip/sdram_common.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GRF_BASE 0xff770000
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#ifdef CONFIG_SPL_BUILD
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static void configure_l2ctlr(void)
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{
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u32 l2ctlr;
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l2ctlr = read_l2ctlr();
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l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
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/*
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* Data RAM write latency: 2 cycles
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* Data RAM read latency: 2 cycles
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* Data RAM setup latency: 1 cycle
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* Tag RAM write latency: 1 cycle
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* Tag RAM read latency: 1 cycle
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* Tag RAM setup latency: 1 cycle
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*/
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l2ctlr |= (1 << 3 | 1 << 0);
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write_l2ctlr(l2ctlr);
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}
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#endif
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int arch_cpu_init(void)
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{
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#ifdef CONFIG_SPL_BUILD
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configure_l2ctlr();
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#else
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/* We do some SoC one time setting here. */
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struct rk3288_grf * const grf = (void *)GRF_BASE;
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/* Use rkpwm by default */
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rk_setreg(&grf->soc_con2, 1 << 0);
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#endif
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return 0;
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}
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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/* Enable early UART on the RK3288 */
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struct rk3288_grf * const grf = (void *)GRF_BASE;
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rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
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GPIO7C6_MASK << GPIO7C6_SHIFT,
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GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
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GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
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}
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#endif
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#ifdef CONFIG_SPL_OS_BOOT
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#define PMU_BASE 0xff730000
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int dram_init_banksize(void)
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{
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struct rk3288_pmu *const pmu = (void *)PMU_BASE;
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size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = size;
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return 0;
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}
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#endif
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