mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 16:10:58 +00:00
2cddfcbc75
i.MX8MM/MN/MP/MQ - added support for JR driver model. sec is initialized based on job ring information processed from device tree. Signed-off-by: Gaurav Jain <gaurav.jain@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
172 lines
3.7 KiB
C
172 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
/*
|
|
* Copyright 2018-2019, 2021 NXP
|
|
*
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <command.h>
|
|
#include <cpu_func.h>
|
|
#include <hang.h>
|
|
#include <image.h>
|
|
#include <init.h>
|
|
#include <log.h>
|
|
#include <spl.h>
|
|
#include <asm/global_data.h>
|
|
#include <asm/io.h>
|
|
#include <asm/mach-imx/iomux-v3.h>
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/imx8mn_pins.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <asm/mach-imx/boot_mode.h>
|
|
#include <asm/arch/ddr.h>
|
|
|
|
#include <dm/uclass.h>
|
|
#include <dm/device.h>
|
|
#include <dm/uclass-internal.h>
|
|
#include <dm/device-internal.h>
|
|
#include <power/pmic.h>
|
|
#include <power/pca9450.h>
|
|
#include <asm/mach-imx/gpio.h>
|
|
#include <asm/mach-imx/mxc_i2c.h>
|
|
#include <fsl_esdhc_imx.h>
|
|
#include <mmc.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int spl_board_boot_device(enum boot_device boot_dev_spl)
|
|
{
|
|
return BOOT_DEVICE_BOOTROM;
|
|
}
|
|
|
|
void spl_dram_init(void)
|
|
{
|
|
ddr_init(&dram_timing);
|
|
}
|
|
|
|
void spl_board_init(void)
|
|
{
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
if (IS_ENABLED(CONFIG_FSL_CAAM)) {
|
|
ret = uclass_get_device_by_driver(UCLASS_MISC, DM_DRIVER_GET(caam_jr), &dev);
|
|
if (ret)
|
|
printf("Failed to initialize %s: %d\n", dev->name, ret);
|
|
}
|
|
puts("Normal Boot\n");
|
|
|
|
ret = uclass_get_device_by_name(UCLASS_CLK,
|
|
"clock-controller@30380000",
|
|
&dev);
|
|
if (ret < 0)
|
|
printf("Failed to find clock node. Check device tree\n");
|
|
}
|
|
|
|
#if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
|
|
int power_init_board(void)
|
|
{
|
|
struct udevice *dev;
|
|
int ret;
|
|
|
|
ret = pmic_get("pca9450@25", &dev);
|
|
if (ret == -ENODEV) {
|
|
puts("No pca9450@25\n");
|
|
return 0;
|
|
}
|
|
if (ret != 0)
|
|
return ret;
|
|
|
|
/* BUCKxOUT_DVS0/1 control BUCK123 output */
|
|
pmic_reg_write(dev, PCA9450_BUCK123_DVS, 0x29);
|
|
|
|
#ifdef CONFIG_IMX8MN_LOW_DRIVE_MODE
|
|
/* Set VDD_SOC/VDD_DRAM to 0.8v for low drive mode */
|
|
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x10);
|
|
#else
|
|
/* increase VDD_SOC/VDD_DRAM to typical value 0.95V before first DRAM access */
|
|
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS0, 0x1C);
|
|
#endif
|
|
/* Set DVS1 to 0.85v for suspend */
|
|
/* Enable DVS control through PMIC_STBY_REQ and set B1_ENMODE=1 (ON by PMIC_ON_REQ=H) */
|
|
pmic_reg_write(dev, PCA9450_BUCK1OUT_DVS1, 0x14);
|
|
pmic_reg_write(dev, PCA9450_BUCK1CTRL, 0x59);
|
|
|
|
/* set VDD_SNVS_0V8 from default 0.85V */
|
|
pmic_reg_write(dev, PCA9450_LDO2CTRL, 0xC0);
|
|
|
|
/* enable LDO4 to 1.2v */
|
|
pmic_reg_write(dev, PCA9450_LDO4CTRL, 0x44);
|
|
|
|
/* set WDOG_B_CFG to cold reset */
|
|
pmic_reg_write(dev, PCA9450_RESET_CTRL, 0xA1);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_SPL_LOAD_FIT
|
|
int board_fit_config_name_match(const char *name)
|
|
{
|
|
/* Just empty function now - can't decide what to choose */
|
|
debug("%s: %s\n", __func__, name);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1)
|
|
#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_ODE | PAD_CTL_PUE | PAD_CTL_PE)
|
|
|
|
static iomux_v3_cfg_t const uart_pads[] = {
|
|
IMX8MN_PAD_UART2_RXD__UART2_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
IMX8MN_PAD_UART2_TXD__UART2_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
|
|
};
|
|
|
|
static iomux_v3_cfg_t const wdog_pads[] = {
|
|
IMX8MN_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL),
|
|
};
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR;
|
|
|
|
imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads));
|
|
|
|
set_wdog_reset(wdog);
|
|
|
|
imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
|
|
|
|
return 0;
|
|
}
|
|
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
int ret;
|
|
|
|
arch_cpu_init();
|
|
|
|
init_uart_clk(1);
|
|
|
|
board_early_init_f();
|
|
|
|
timer_init();
|
|
|
|
preloader_console_init();
|
|
|
|
/* Clear the BSS. */
|
|
memset(__bss_start, 0, __bss_end - __bss_start);
|
|
|
|
ret = spl_init();
|
|
if (ret) {
|
|
debug("spl_init() failed: %d\n", ret);
|
|
hang();
|
|
}
|
|
|
|
enable_tzc380();
|
|
|
|
/* DDR initialization */
|
|
spl_dram_init();
|
|
|
|
board_init_r(NULL, 0);
|
|
}
|