mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 09:27:35 +00:00
fbe127f7b5
Import updated devicetree files from the Linux v5.12 release. Besides some node and audio port renames this changes the PHY modes to either rgmii-id or rgmii-txid. From the board files the Pinephone sees a lot of updates. This also adds the long missing USB PHY property for controller 0, which allows the U-Boot PHY driver to eventually use port 0 in host mode (pending another U-Boot patch). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
137 lines
2.6 KiB
Text
137 lines
2.6 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
// Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.xyz>
|
|
// Based on sun50i-a64-pine64.dts, which is:
|
|
// Copyright (c) 2016 ARM Ltd.
|
|
|
|
#include "sun50i-a64.dtsi"
|
|
#include "sun50i-a64-cpu-opp.dtsi"
|
|
|
|
#include <dt-bindings/gpio/gpio.h>
|
|
|
|
&codec_analog {
|
|
cpvdd-supply = <®_eldo1>;
|
|
};
|
|
|
|
&cpu0 {
|
|
cpu-supply = <®_dcdc2>;
|
|
};
|
|
|
|
&cpu1 {
|
|
cpu-supply = <®_dcdc2>;
|
|
};
|
|
|
|
&cpu2 {
|
|
cpu-supply = <®_dcdc2>;
|
|
};
|
|
|
|
&cpu3 {
|
|
cpu-supply = <®_dcdc2>;
|
|
};
|
|
|
|
&mmc0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&mmc0_pins>;
|
|
vmmc-supply = <®_dcdc1>;
|
|
disable-wp;
|
|
bus-width = <4>;
|
|
cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 push-pull switch */
|
|
status = "okay";
|
|
};
|
|
|
|
&r_rsb {
|
|
status = "okay";
|
|
|
|
axp803: pmic@3a3 {
|
|
compatible = "x-powers,axp803";
|
|
reg = <0x3a3>;
|
|
interrupt-parent = <&r_intc>;
|
|
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
};
|
|
|
|
&spi0 {
|
|
status = "okay";
|
|
|
|
flash@0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <40000000>;
|
|
};
|
|
};
|
|
|
|
#include "axp803.dtsi"
|
|
|
|
®_aldo2 {
|
|
regulator-always-on;
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-name = "vcc-pl";
|
|
};
|
|
|
|
®_aldo3 {
|
|
regulator-always-on;
|
|
regulator-min-microvolt = <3000000>;
|
|
regulator-max-microvolt = <3000000>;
|
|
regulator-name = "vcc-pll-avcc";
|
|
};
|
|
|
|
®_dcdc1 {
|
|
regulator-always-on;
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-name = "vcc-3v3";
|
|
};
|
|
|
|
®_dcdc2 {
|
|
regulator-always-on;
|
|
regulator-min-microvolt = <1040000>;
|
|
regulator-max-microvolt = <1300000>;
|
|
regulator-name = "vdd-cpux";
|
|
};
|
|
|
|
/* DCDC3 is polyphased with DCDC2 */
|
|
|
|
®_dcdc5 {
|
|
regulator-always-on;
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-name = "vcc-dram";
|
|
};
|
|
|
|
®_dcdc6 {
|
|
regulator-always-on;
|
|
regulator-min-microvolt = <1100000>;
|
|
regulator-max-microvolt = <1100000>;
|
|
regulator-name = "vdd-sys";
|
|
};
|
|
|
|
®_eldo1 {
|
|
regulator-always-on;
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-name = "vdd-1v8-lpddr";
|
|
};
|
|
|
|
®_fldo1 {
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-name = "vcc-1v2-hsic";
|
|
};
|
|
|
|
/*
|
|
* The A64 chip cannot work without this regulator off, although
|
|
* it seems to be only driving the AR100 core.
|
|
* Maybe we don't still know well about CPUs domain.
|
|
*/
|
|
®_fldo2 {
|
|
regulator-always-on;
|
|
regulator-min-microvolt = <1100000>;
|
|
regulator-max-microvolt = <1100000>;
|
|
regulator-name = "vdd-cpus";
|
|
};
|
|
|
|
®_rtc_ldo {
|
|
regulator-name = "vcc-rtc";
|
|
};
|