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https://github.com/AsahiLinux/u-boot
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95ca100ba7
mmc using 150000000 as max-frequency like what rk3288 sets. This can speed up the mmc read/write, the actual mmc clock is: Before this patch: 37.125M After this patch: 49.5M Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
782 lines
19 KiB
Text
782 lines
19 KiB
Text
/*
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* Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/rockchip.h>
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#include <dt-bindings/clock/rk3228-cru.h>
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#include <dt-bindings/thermal/thermal.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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mmc0 = &emmc;
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mmc1 = &sdmmc;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@f00 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf00>;
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resets = <&cru SRST_CORE0>;
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operating-points = <
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/* KHz uV */
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816000 1000000
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>;
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#cooling-cells = <2>; /* min followed by max */
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clock-latency = <40000>;
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clocks = <&cru ARMCLK>;
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};
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cpu1: cpu@f01 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf01>;
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resets = <&cru SRST_CORE1>;
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};
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cpu2: cpu@f02 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf02>;
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resets = <&cru SRST_CORE2>;
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};
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cpu3: cpu@f03 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0xf03>;
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resets = <&cru SRST_CORE3>;
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};
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};
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amba {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pdma: pdma@110f0000 {
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compatible = "arm,pl330", "arm,primecell";
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reg = <0x110f0000 0x4000>;
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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#dma-cells = <1>;
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clocks = <&cru ACLK_DMAC>;
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clock-names = "apb_pclk";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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timer {
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compatible = "arm,armv7-timer";
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arm,cpu-registers-not-fw-configured;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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clock-frequency = <24000000>;
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};
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xin24m: oscillator {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xin24m";
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#clock-cells = <0>;
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};
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bus_intmem@10080000 {
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compatible = "mmio-sram";
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reg = <0x10080000 0x9000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x10080000 0x9000>;
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smp-sram@0 {
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compatible = "rockchip,rk322x-smp-sram";
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reg = <0x00 0x10>;
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};
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ddr_sram: ddr-sram@1000 {
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compatible = "rockchip,rk322x-ddr-sram";
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reg = <0x1000 0x8000>;
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};
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};
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i2s1: i2s1@100b0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100b0000 0x4000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
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dmas = <&pdma 14>, <&pdma 15>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&i2s1_bus>;
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status = "disabled";
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};
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i2s0: i2s0@100c0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100c0000 0x4000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
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dmas = <&pdma 11>, <&pdma 12>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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i2s2: i2s2@100e0000 {
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compatible = "rockchip,rk3228-i2s", "rockchip,rk3066-i2s";
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reg = <0x100e0000 0x4000>;
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interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2s_clk", "i2s_hclk";
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clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
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dmas = <&pdma 0>, <&pdma 1>;
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dma-names = "tx", "rx";
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status = "disabled";
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};
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grf: syscon@11000000 {
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u-boot,dm-pre-reloc;
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compatible = "rockchip,rk3228-grf", "syscon";
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reg = <0x11000000 0x1000>;
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};
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uart0: serial@11010000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x11010000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart1: serial@11020000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x11020000 0x100>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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uart2: serial@11030000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x11030000 0x100>;
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <24000000>;
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clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
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clock-names = "baudclk", "apb_pclk";
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_xfer>;
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reg-shift = <2>;
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reg-io-width = <4>;
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status = "disabled";
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};
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i2c0: i2c@11050000 {
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compatible = "rockchip,rk3228-i2c";
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reg = <0x11050000 0x1000>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C0>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c0_xfer>;
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status = "disabled";
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};
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i2c1: i2c@11060000 {
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compatible = "rockchip,rk3228-i2c";
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reg = <0x11060000 0x1000>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C1>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c1_xfer>;
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status = "disabled";
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};
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i2c2: i2c@11070000 {
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compatible = "rockchip,rk3228-i2c";
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reg = <0x11070000 0x1000>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C2>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c2_xfer>;
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status = "disabled";
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};
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i2c3: i2c@11080000 {
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compatible = "rockchip,rk3228-i2c";
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reg = <0x11080000 0x1000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "i2c";
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clocks = <&cru PCLK_I2C3>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c3_xfer>;
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status = "disabled";
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};
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pwm0: pwm@110b0000 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0x110b0000 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm0_pin>;
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status = "disabled";
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};
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pwm1: pwm@110b0010 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0x110b0010 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm1_pin>;
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status = "disabled";
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};
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pwm2: pwm@110b0020 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0x110b0020 0x10>;
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#pwm-cells = <3>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm2_pin>;
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status = "disabled";
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};
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pwm3: pwm@110b0030 {
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compatible = "rockchip,rk3288-pwm";
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reg = <0x110b0030 0x10>;
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#pwm-cells = <2>;
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clocks = <&cru PCLK_PWM>;
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clock-names = "pwm";
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pinctrl-names = "default";
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pinctrl-0 = <&pwm3_pin>;
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status = "disabled";
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};
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timer: timer@110c0000 {
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compatible = "rockchip,rk3288-timer";
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reg = <0x110c0000 0x20>;
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&xin24m>, <&cru PCLK_TIMER>;
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clock-names = "timer", "pclk";
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};
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cru: clock-controller@110e0000 {
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u-boot,dm-pre-reloc;
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compatible = "rockchip,rk3228-cru";
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reg = <0x110e0000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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assigned-clocks = <&cru PLL_GPLL>;
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assigned-clock-rates = <594000000>;
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};
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thermal-zones {
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cpu_thermal: cpu-thermal {
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polling-delay-passive = <100>; /* milliseconds */
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polling-delay = <5000>; /* milliseconds */
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thermal-sensors = <&tsadc 0>;
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trips {
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cpu_alert0: cpu_alert0 {
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temperature = <70000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_alert1: cpu_alert1 {
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temperature = <75000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "passive";
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};
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cpu_crit: cpu_crit {
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temperature = <90000>; /* millicelsius */
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hysteresis = <2000>; /* millicelsius */
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type = "critical";
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};
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};
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cooling-maps {
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map0 {
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trip = <&cpu_alert0>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT 6>;
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};
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map1 {
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trip = <&cpu_alert1>;
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cooling-device =
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<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
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};
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};
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};
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};
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tsadc: tsadc@11150000 {
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compatible = "rockchip,rk3228-tsadc";
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reg = <0x11150000 0x100>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
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clock-names = "tsadc", "apb_pclk";
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resets = <&cru SRST_TSADC>;
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reset-names = "tsadc-apb";
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pinctrl-names = "init", "default", "sleep";
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pinctrl-0 = <&otp_gpio>;
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pinctrl-1 = <&otp_out>;
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pinctrl-2 = <&otp_gpio>;
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#thermal-sensor-cells = <0>;
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rockchip,hw-tshut-temp = <95000>;
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status = "disabled";
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};
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sdmmc: dwmmc@30000000 {
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compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x30000000 0x4000>;
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max-frequency = <150000000>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
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<&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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fifo-depth = <0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
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status = "disabled";
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};
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sdio: dwmmc@30010000 {
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compatible = "rockchip,rk3228-dw-mshc", "rockchip,rk3288-dw-mshc";
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reg = <0x30010000 0x4000>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
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<&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
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clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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fifo-depth = <0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&sdio_clk &sdio_cmd &sdio_bus4>;
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status = "disabled";
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};
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emmc: dwmmc@30020000 {
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compatible = "rockchip,rk3288-dw-mshc";
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reg = <0x30020000 0x4000>;
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max-frequency = <150000000>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
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<&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
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clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
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bus-width = <8>;
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default-sample-phase = <158>;
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num-slots = <1>;
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fifo-depth = <0x100>;
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
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resets = <&cru SRST_EMMC>;
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reset-names = "reset";
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status = "disabled";
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};
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usb20_otg: usb@30040000 {
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compatible = "rockchip,rk3229-usb", "rockchip,rk3288-usb",
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"snps,dwc2";
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reg = <0x30040000 0x40000>;
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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hnp-srp-disable;
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dr_mode = "otg";
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status = "disabled";
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};
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gmac: ethernet@30200000 {
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compatible = "rockchip,rk3228-gmac";
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reg = <0x30200000 0x10000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "macirq";
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clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
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<&cru SCLK_MAC_TX>, <&cru SCLK_MAC_REF>,
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<&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>,
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<&cru PCLK_GMAC>;
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clock-names = "stmmaceth", "mac_clk_rx",
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"mac_clk_tx", "clk_mac_ref",
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"clk_mac_refout", "aclk_mac",
|
|
"pclk_mac";
|
|
resets = <&cru SRST_GMAC>;
|
|
reset-names = "stmmaceth";
|
|
rockchip,grf = <&grf>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@32010000 {
|
|
compatible = "arm,gic-400";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
|
|
reg = <0x32011000 0x1000>,
|
|
<0x32012000 0x2000>,
|
|
<0x32014000 0x2000>,
|
|
<0x32016000 0x2000>;
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
};
|
|
|
|
pinctrl: pinctrl {
|
|
compatible = "rockchip,rk3228-pinctrl";
|
|
rockchip,grf = <&grf>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
gpio0: gpio0@11110000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x11110000 0x100>;
|
|
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO0>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio1@11120000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x11120000 0x100>;
|
|
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO1>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio2@11130000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x11130000 0x100>;
|
|
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO2>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio3@11140000 {
|
|
compatible = "rockchip,gpio-bank";
|
|
reg = <0x11140000 0x100>;
|
|
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cru PCLK_GPIO3>;
|
|
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
pcfg_pull_up: pcfg-pull-up {
|
|
bias-pull-up;
|
|
};
|
|
|
|
pcfg_pull_down: pcfg-pull-down {
|
|
bias-pull-down;
|
|
};
|
|
|
|
pcfg_pull_none: pcfg-pull-none {
|
|
bias-disable;
|
|
};
|
|
|
|
pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
|
|
drive-strength = <12>;
|
|
};
|
|
|
|
sdmmc {
|
|
sdmmc_clk: sdmmc-clk {
|
|
rockchip,pins = <1 16 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
|
|
};
|
|
|
|
sdmmc_cmd: sdmmc-cmd {
|
|
rockchip,pins = <1 15 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
|
|
};
|
|
|
|
sdmmc_bus4: sdmmc-bus4 {
|
|
rockchip,pins = <1 18 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<1 19 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<1 20 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<1 21 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
|
|
};
|
|
};
|
|
|
|
sdio {
|
|
sdio_clk: sdio-clk {
|
|
rockchip,pins = <3 0 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
|
|
};
|
|
|
|
sdio_cmd: sdio-cmd {
|
|
rockchip,pins = <3 1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
|
|
};
|
|
|
|
sdio_bus4: sdio-bus4 {
|
|
rockchip,pins = <3 2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<3 3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<3 4 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<3 5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>;
|
|
};
|
|
};
|
|
|
|
emmc {
|
|
emmc_clk: emmc-clk {
|
|
rockchip,pins = <2 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_cmd: emmc-cmd {
|
|
rockchip,pins = <1 RK_PC6 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
emmc_bus8: emmc-bus8 {
|
|
rockchip,pins = <1 RK_PD0 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 RK_PD1 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 RK_PD2 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 RK_PD3 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 RK_PD6 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 RK_PD7 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
gmac {
|
|
rgmii_pins: rgmii-pins {
|
|
rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 RK_PC6 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 RK_PC7 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 RK_PB1 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PC5 RK_FUNC_2 &pcfg_pull_none>,
|
|
<2 RK_PC4 RK_FUNC_2 &pcfg_pull_none>,
|
|
<2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
rmii_pins: rmii-pins {
|
|
rockchip,pins = <2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none_drv_12ma>,
|
|
<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
phy_pins: phy-pins {
|
|
rockchip,pins = <2 RK_PB6 RK_FUNC_2 &pcfg_pull_none>,
|
|
<2 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
i2c0_xfer: i2c0-xfer {
|
|
rockchip,pins = <0 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 RK_PA1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
i2c1_xfer: i2c1-xfer {
|
|
rockchip,pins = <0 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
i2c2_xfer: i2c2-xfer {
|
|
rockchip,pins = <2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2c3 {
|
|
i2c3_xfer: i2c3-xfer {
|
|
rockchip,pins = <0 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 RK_PA7 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
i2s1 {
|
|
i2s1_bus: i2s1-bus {
|
|
rockchip,pins = <0 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,
|
|
<0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
|
|
<1 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,
|
|
<1 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,
|
|
<1 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm0 {
|
|
pwm0_pin: pwm0-pin {
|
|
rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm1 {
|
|
pwm1_pin: pwm1-pin {
|
|
rockchip,pins = <0 RK_PD6 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm2 {
|
|
pwm2_pin: pwm2-pin {
|
|
rockchip,pins = <1 RK_PB4 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
pwm3 {
|
|
pwm3_pin: pwm3-pin {
|
|
rockchip,pins = <1 RK_PB3 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
tsadc {
|
|
otp_gpio: otp-gpio {
|
|
rockchip,pins = <0 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
|
|
};
|
|
|
|
otp_out: otp-out {
|
|
rockchip,pins = <0 RK_PD0 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart0 {
|
|
uart0_xfer: uart0-xfer {
|
|
rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>,
|
|
<2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_cts: uart0-cts {
|
|
rockchip,pins = <2 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart0_rts: uart0-rts {
|
|
rockchip,pins = <0 RK_PC1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart1 {
|
|
uart1_xfer: uart1-xfer {
|
|
rockchip,pins = <1 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,
|
|
<1 RK_PB2 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_cts: uart1-cts {
|
|
rockchip,pins = <1 RK_PB0 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart1_rts: uart1-rts {
|
|
rockchip,pins = <1 RK_PB3 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
|
|
uart2 {
|
|
uart2_xfer: uart2-xfer {
|
|
rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
|
|
<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart2_cts: uart2-cts {
|
|
rockchip,pins = <0 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
|
|
uart2_rts: uart2-rts {
|
|
rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
|
|
};
|
|
};
|
|
};
|
|
|
|
dmc: dmc@11200000 {
|
|
u-boot,dm-pre-reloc;
|
|
compatible = "rockchip,rk3228-dmc", "syscon";
|
|
rockchip,cru = <&cru>;
|
|
rockchip,grf = <&grf>;
|
|
rockchip,msch = <&service_msch>;
|
|
reg = <0x11200000 0x3fc
|
|
0x12000000 0x400>;
|
|
rockchip,sram = <&ddr_sram>;
|
|
};
|
|
|
|
service_msch: syscon@31090000 {
|
|
u-boot,dm-pre-reloc;
|
|
compatible = "rockchip,rk3228-msch", "syscon";
|
|
reg = <0x31090000 0x2000>;
|
|
};
|
|
};
|