mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
211 lines
5.6 KiB
C
211 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <asm/arch/ls102xa_stream_id.h>
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#include <fsl_csu.h>
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struct liodn_id_table sec_liodn_tbl[] = {
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SET_SEC_JR_LIODN_ENTRY(0, 0x10, 0x10),
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SET_SEC_JR_LIODN_ENTRY(1, 0x10, 0x10),
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SET_SEC_JR_LIODN_ENTRY(2, 0x10, 0x10),
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SET_SEC_JR_LIODN_ENTRY(3, 0x10, 0x10),
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SET_SEC_RTIC_LIODN_ENTRY(a, 0x10),
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SET_SEC_RTIC_LIODN_ENTRY(b, 0x10),
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SET_SEC_RTIC_LIODN_ENTRY(c, 0x10),
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SET_SEC_RTIC_LIODN_ENTRY(d, 0x10),
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SET_SEC_DECO_LIODN_ENTRY(0, 0x10, 0x10),
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SET_SEC_DECO_LIODN_ENTRY(1, 0x10, 0x10),
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SET_SEC_DECO_LIODN_ENTRY(2, 0x10, 0x10),
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SET_SEC_DECO_LIODN_ENTRY(3, 0x10, 0x10),
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SET_SEC_DECO_LIODN_ENTRY(4, 0x10, 0x10),
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SET_SEC_DECO_LIODN_ENTRY(5, 0x10, 0x10),
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SET_SEC_DECO_LIODN_ENTRY(6, 0x10, 0x10),
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SET_SEC_DECO_LIODN_ENTRY(7, 0x10, 0x10),
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};
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struct smmu_stream_id dev_stream_id[] = {
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{ 0x100, 0x01, "ETSEC MAC1" },
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{ 0x104, 0x02, "ETSEC MAC2" },
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{ 0x108, 0x03, "ETSEC MAC3" },
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{ 0x10c, 0x04, "PEX1" },
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{ 0x110, 0x05, "PEX2" },
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{ 0x114, 0x06, "qDMA" },
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{ 0x118, 0x07, "SATA" },
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{ 0x11c, 0x08, "USB3" },
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{ 0x120, 0x09, "QE" },
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{ 0x124, 0x0a, "eSDHC" },
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{ 0x128, 0x0b, "eMA" },
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{ 0x14c, 0x0c, "2D-ACE" },
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{ 0x150, 0x0d, "USB2" },
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{ 0x18c, 0x0e, "DEBUG" },
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};
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unsigned int get_soc_major_rev(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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unsigned int svr, major;
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svr = in_be32(&gur->svr);
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major = SVR_MAJ(svr);
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return major;
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}
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static void erratum_a009008(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
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u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
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clrsetbits_be32(scfg + SCFG_USB3PRM1CR / 4,
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0xF << 6,
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SCFG_USB_TXVREFTUNE << 6);
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#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
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}
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static void erratum_a009798(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
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u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
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clrbits_be32(scfg + SCFG_USB3PRM1CR / 4,
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SCFG_USB_SQRXTUNE_MASK << 23);
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#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
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}
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static void erratum_a008997(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
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u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
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clrsetbits_be32(scfg + SCFG_USB3PRM2CR / 4,
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SCFG_USB_PCSTXSWINGFULL_MASK,
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SCFG_USB_PCSTXSWINGFULL_VAL);
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#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
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}
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static void erratum_a009007(void)
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
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void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
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out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
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out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
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out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
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out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
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#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
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}
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void s_init(void)
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{
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}
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#ifdef CONFIG_SYS_FSL_ERRATUM_A010315
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void erratum_a010315(void)
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{
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int i;
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for (i = PCIE1; i <= PCIE2; i++)
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if (!is_serdes_configured(i)) {
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debug("PCIe%d: disabled all R/W permission!\n", i);
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set_pcie_ns_access(i, 0);
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}
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}
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#endif
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int arch_soc_init(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
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struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
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CONFIG_SYS_CCI400_OFFSET);
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unsigned int major;
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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#ifdef CONFIG_FSL_QSPI
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out_be32(&scfg->qspi_cfg, SCFG_QSPI_CLKSEL);
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#endif
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#ifdef CONFIG_VIDEO_FSL_DCU_FB
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out_be32(&scfg->pixclkcr, SCFG_PIXCLKCR_PXCKEN);
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#endif
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/* Configure Little endian for SAI, ASRC and SPDIF */
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out_be32(&scfg->endiancr, SCFG_ENDIANCR_LE);
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/*
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* Enable snoop requests and DVM message requests for
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* All the slave insterfaces.
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*/
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out_le32(&cci->slave[0].snoop_ctrl,
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CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
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out_le32(&cci->slave[1].snoop_ctrl,
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CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
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out_le32(&cci->slave[2].snoop_ctrl,
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CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
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out_le32(&cci->slave[4].snoop_ctrl,
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CCI400_DVM_MESSAGE_REQ_EN | CCI400_SNOOP_REQ_EN);
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major = get_soc_major_rev();
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if (major == SOC_MAJOR_VER_1_0) {
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/*
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* Set CCI-400 Slave interface S1, S2 Shareable Override
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* Register All transactions are treated as non-shareable
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*/
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out_le32(&cci->slave[1].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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out_le32(&cci->slave[2].sha_ord, CCI400_SHAORD_NON_SHAREABLE);
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/* Workaround for the issue that DDR could not respond to
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* barrier transaction which is generated by executing DSB/ISB
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* instruction. Set CCI-400 control override register to
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* terminate the barrier transaction. After DDR is initialized,
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* allow barrier transaction to DDR again */
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out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
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}
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/* Enable all the snoop signal for various masters */
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out_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR |
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SCFG_SNPCNFGCR_DCU_RD_WR |
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SCFG_SNPCNFGCR_SATA_RD_WR |
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SCFG_SNPCNFGCR_USB3_RD_WR |
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SCFG_SNPCNFGCR_DBG_RD_WR |
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SCFG_SNPCNFGCR_EDMA_SNP);
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/*
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* Memory controller require a register write before being enabled.
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* Affects: DDR
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* Register: EDDRTQCFG
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* Description: Memory controller performance is not optimal with
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* default internal target queue register values.
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* Workaround: Write a value of 63b2_0042h to address: 157_020Ch.
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*/
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out_be32(&scfg->eddrtqcfg, 0x63b20042);
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/* Erratum */
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erratum_a009008();
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erratum_a009798();
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erratum_a008997();
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erratum_a009007();
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return 0;
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}
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int ls102xa_smmu_stream_id_init(void)
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{
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ls1021x_config_caam_stream_id(sec_liodn_tbl,
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ARRAY_SIZE(sec_liodn_tbl));
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ls102xa_config_smmu_stream_id(dev_stream_id,
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ARRAY_SIZE(dev_stream_id));
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return 0;
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}
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