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f2b37a6533
The PLL setup values currently assume a 24 Mhz input clock. This patch uses V_OSCK from the board config file to support boards with different input clock rates. Signed-off-by: Steve Sakoman <steve@sakoman.com> |
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.. | ||
cpu | ||
dts | ||
include/asm | ||
lib | ||
config.mk |