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https://github.com/AsahiLinux/u-boot
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
157 lines
3.5 KiB
ArmAsm
157 lines
3.5 KiB
ArmAsm
/*
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* For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
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* Applications Processor Reference Manual, Rev. 0.2".
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*
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* (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
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* (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/macro.h>
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#include <asm/arch/imx-regs.h>
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#include <generated/asm-offsets.h>
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SOC_ESDCTL_BASE_W: .word IMX_ESD_BASE
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SOC_SI_ID_REG_W: .word IMX_SYSTEM_CTL_BASE
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SDRAM_ESDCFG_T1_W: .word SDRAM_ESDCFG_REGISTER_VAL(0)
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SDRAM_ESDCFG_T2_W: .word SDRAM_ESDCFG_REGISTER_VAL(3)
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SDRAM_PRECHARGE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
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ESDCTL_ROW13 | ESDCTL_COL10)
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SDRAM_AUTOREF_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
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ESDCTL_ROW13 | ESDCTL_COL10)
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SDRAM_LOADMODE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
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ESDCTL_ROW13 | ESDCTL_COL10)
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SDRAM_NORMAL_CMD_W: .word SDRAM_ESDCTL_REGISTER_VAL
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.macro init_aipi
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/*
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* setup AIPI1 and AIPI2
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*/
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write32 AIPI1_PSR0, AIPI1_PSR0_VAL
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write32 AIPI1_PSR1, AIPI1_PSR1_VAL
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write32 AIPI2_PSR0, AIPI2_PSR0_VAL
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write32 AIPI2_PSR1, AIPI2_PSR1_VAL
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.endm /* init_aipi */
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.macro init_clock
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ldr r0, =CSCR
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/* disable MPLL/SPLL first */
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ldr r1, [r0]
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bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
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str r1, [r0]
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write32 MPCTL0, MPCTL0_VAL
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write32 SPCTL0, SPCTL0_VAL
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write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
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/*
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* add some delay here
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*/
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wait_timer 0x1000
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/* peripheral clock divider */
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write32 PCDR0, PCDR0_VAL
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write32 PCDR1, PCDR1_VAL
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/* Configure PCCR0 and PCCR1 */
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write32 PCCR0, PCCR0_VAL
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write32 PCCR1, PCCR1_VAL
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.endm /* init_clock */
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.macro sdram_init
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ldr r0, SOC_ESDCTL_BASE_W
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mov r2, #PHYS_SDRAM_1
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/* Do initial reset */
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mov r1, #ESDMISC_MDDR_DL_RST
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str r1, [r0, #ESDMISC_ROF]
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/* Hold for more than 200ns */
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wait_timer 0x10000
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/* Activate LPDDR iface */
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mov r1, #ESDMISC_MDDREN
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str r1, [r0, #ESDMISC_ROF]
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/* Check The chip version TO1 or TO2 */
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ldr r1, SOC_SI_ID_REG_W
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ldr r1, [r1]
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ands r1, r1, #0xF0000000
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/* add Latency on CAS only for TO2 */
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ldreq r1, SDRAM_ESDCFG_T2_W
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ldrne r1, SDRAM_ESDCFG_T1_W
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str r1, [r0, #ESDCFG0_ROF]
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/* Run initialization sequence */
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ldr r1, SDRAM_PRECHARGE_CMD_W
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str r1, [r0, #ESDCTL0_ROF]
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ldr r1, [r2, #SDRAM_ALL_VAL]
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ldr r1, SDRAM_AUTOREF_CMD_W
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str r1, [r0, #ESDCTL0_ROF]
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ldr r1, [r2, #SDRAM_ALL_VAL]
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ldr r1, [r2, #SDRAM_ALL_VAL]
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ldr r1, SDRAM_LOADMODE_CMD_W
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str r1, [r0, #ESDCTL0_ROF]
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ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
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add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
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ldrb r1, [r3]
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ldr r1, SDRAM_NORMAL_CMD_W
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str r1, [r0, #ESDCTL0_ROF]
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#if (CONFIG_NR_DRAM_BANKS > 1)
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/* 2nd sdram */
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mov r2, #PHYS_SDRAM_2
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/* Check The chip version TO1 or TO2 */
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ldr r1, SOC_SI_ID_REG_W
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ldr r1, [r1]
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ands r1, r1, #0xF0000000
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/* add Latency on CAS only for TO2 */
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ldreq r1, SDRAM_ESDCFG_T2_W
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ldrne r1, SDRAM_ESDCFG_T1_W
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str r1, [r0, #ESDCFG1_ROF]
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/* Run initialization sequence */
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ldr r1, SDRAM_PRECHARGE_CMD_W
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str r1, [r0, #ESDCTL1_ROF]
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ldr r1, [r2, #SDRAM_ALL_VAL]
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ldr r1, SDRAM_AUTOREF_CMD_W
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str r1, [r0, #ESDCTL1_ROF]
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ldr r1, [r2, #SDRAM_ALL_VAL]
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ldr r1, [r2, #SDRAM_ALL_VAL]
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ldr r1, SDRAM_LOADMODE_CMD_W
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str r1, [r0, #ESDCTL1_ROF]
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ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
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add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
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ldrb r1, [r3]
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ldr r1, SDRAM_NORMAL_CMD_W
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str r1, [r0, #ESDCTL1_ROF]
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#endif /* CONFIG_NR_DRAM_BANKS > 1 */
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.endm /* sdram_init */
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.globl lowlevel_init
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lowlevel_init:
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mov r10, lr
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init_aipi
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init_clock
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sdram_init
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mov pc,r10
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