Bin Meng 3c85099aa3 riscv: bootm: Change to use boot_hart from global data ... Avoid reading mhartid CSR directly, instead use the one we saved in the global data structure before. With this patch, BBL no longer needs to be hacked to provide the mhartid CSR emulation for S-mode U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>		2018-12-18 09:56:27 +08:00
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asm-offsets.c	riscv: Save boot hart id to the global data	2018-12-18 09:56:27 +08:00
boot.c	SPDX: Convert all of our single license tags to Linux Kernel style	2018-05-07 09:34:12 -04:00
bootm.c	riscv: bootm: Change to use boot_hart from global data	2018-12-18 09:56:27 +08:00
cache.c	riscv: cache: Implement i/dcache [status, enable, disable]	2018-11-26 13:58:01 +08:00
crt0_riscv_efi.S	riscv: efi: Generate Microsoft PE format compliant images	2018-12-02 21:59:36 +01:00
elf_riscv32_efi.lds	SPDX: Convert single license tags to Linux Kernel style	2018-05-29 14:44:21 +08:00
elf_riscv64_efi.lds	SPDX: Convert single license tags to Linux Kernel style	2018-05-29 14:44:21 +08:00
interrupts.c	riscv: Adjust the _exit_trap() position to come before handle_trap()	2018-12-18 09:56:27 +08:00
Makefile	riscv: Implement riscv_get_time() API using rdtime instruction	2018-12-18 09:56:27 +08:00
rdtime.c	riscv: Implement riscv_get_time() API using rdtime instruction	2018-12-18 09:56:27 +08:00
reloc_riscv_efi.c	riscv: Remove unused _relocate arguments	2018-07-19 16:31:37 -04:00
reset.c	riscv: cosmetic: Reword do_reset() printf message.	2018-10-03 17:49:27 +08:00
setjmp.S	riscv: rename CPU_RISCV_32/64 to match architecture names ARCH_RV32I/64I	2018-11-26 13:57:29 +08:00
sifive_clint.c	riscv: Add a SYSCON driver for SiFive's Core Local Interruptor	2018-12-18 09:56:26 +08:00