mirror of
https://github.com/AsahiLinux/u-boot
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401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
213 lines
4.9 KiB
C
213 lines
4.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* vme8349.c -- esd VME8349 board support
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*
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* Copyright (c) 2008-2009 esd gmbh.
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*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
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* Based on board/mpc8349emds/mpc8349emds.c (and previous 834x releases.)
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*/
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#include <common.h>
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#include <fdt_support.h>
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#include <init.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <net.h>
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#include <asm/global_data.h>
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#include <asm/mpc8349_pci.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <linux/libfdt.h>
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#endif
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#include <asm/io.h>
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#include <asm/mmu.h>
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#include <spd.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#include <netdev.h>
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DECLARE_GLOBAL_DATA_PTR;
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void ddr_enable_ecc(unsigned int dram_size);
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int dram_init(void)
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{
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volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -ENXIO;
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/* DDR SDRAM - Main memory */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
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msize = spd_sdram();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* Now check memory size (after ECC is initialized) */
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msize = get_ram_size(0, msize);
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/* return total bus SDRAM size(bytes) -- DDR */
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gd->ram_size = msize * 1024 * 1024;
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return 0;
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}
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int checkboard(void)
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{
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#ifdef CONFIG_TARGET_CADDY2
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puts("Board: esd VME-CADDY/2\n");
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#else
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puts("Board: esd VME-CPU/8349\n");
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#endif
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return 0;
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}
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#ifdef CONFIG_TARGET_CADDY2
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int board_eth_init(struct bd_info *bis)
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{
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return pci_eth_init(bis);
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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#endif
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int misc_init_r()
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{
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immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
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clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
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return 0;
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}
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/*
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* Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
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* and VME-CADDY/2) have different SDRAM configurations.
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*/
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#ifdef CONFIG_TARGET_CADDY2
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#define SMALL_RAM 0xff
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#define LARGE_RAM 0x00
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#else
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#define SMALL_RAM 0x00
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#define LARGE_RAM 0xff
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#endif
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#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
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static spd_eeprom_t default_spd_eeprom = {
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SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
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SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
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SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
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SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
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SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
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SPD_VAL(0x00, 0x00), /* 05 */
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SPD_VAL(0x40, 0x40), /* 06 */
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SPD_VAL(0x00, 0x00), /* 07 */
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SPD_VAL(0x05, 0x05), /* 08 */
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SPD_VAL(0x30, 0x30), /* 09 */
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SPD_VAL(0x45, 0x45), /* 10 */
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SPD_VAL(0x02, 0x02), /* 11 ecc used */
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SPD_VAL(0x82, 0x82), /* 12 */
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SPD_VAL(0x10, 0x10), /* 13 */
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SPD_VAL(0x08, 0x08), /* 14 */
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SPD_VAL(0x00, 0x00), /* 15 */
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SPD_VAL(0x0c, 0x0c), /* 16 */
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SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
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SPD_VAL(0x38, 0x38), /* 18 */
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SPD_VAL(0x00, 0x00), /* 19 */
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SPD_VAL(0x02, 0x02), /* 20 */
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SPD_VAL(0x00, 0x00), /* 21 */
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SPD_VAL(0x03, 0x03), /* 22 */
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SPD_VAL(0x3d, 0x3d), /* 23 */
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SPD_VAL(0x45, 0x45), /* 24 */
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SPD_VAL(0x50, 0x50), /* 25 */
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SPD_VAL(0x45, 0x45), /* 26 */
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SPD_VAL(0x3c, 0x3c), /* 27 */
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SPD_VAL(0x28, 0x28), /* 28 */
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SPD_VAL(0x3c, 0x3c), /* 29 */
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SPD_VAL(0x2d, 0x2d), /* 30 */
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SPD_VAL(0x20, 0x80), /* 31 */
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SPD_VAL(0x20, 0x20), /* 32 */
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SPD_VAL(0x27, 0x27), /* 33 */
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SPD_VAL(0x10, 0x10), /* 34 */
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SPD_VAL(0x17, 0x17), /* 35 */
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SPD_VAL(0x3c, 0x3c), /* 36 */
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SPD_VAL(0x1e, 0x1e), /* 37 */
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SPD_VAL(0x1e, 0x1e), /* 38 */
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SPD_VAL(0x00, 0x00), /* 39 */
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SPD_VAL(0x00, 0x06), /* 40 */
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SPD_VAL(0x37, 0x37), /* 41 */
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SPD_VAL(0x4b, 0x7f), /* 42 */
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SPD_VAL(0x80, 0x80), /* 43 */
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SPD_VAL(0x18, 0x18), /* 44 */
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SPD_VAL(0x22, 0x22), /* 45 */
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SPD_VAL(0x00, 0x00), /* 46 */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
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SPD_VAL(0x10, 0x10), /* 62 */
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SPD_VAL(0x7e, 0x1d), /* 63 */
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{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
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SPD_VAL(0x00, 0x00), /* 72 */
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#ifdef CONFIG_TARGET_CADDY2
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{ "vme-caddy/2 ram " }
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#else
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{ "vme-cpu/2 ram " }
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#endif
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};
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int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
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{
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int old_bus = i2c_get_bus_num();
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unsigned int l, sum;
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int valid = 0;
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i2c_set_bus_num(0);
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if (i2c_read(chip, addr, alen, buffer, len) == 0)
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if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
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sum = 0;
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for (l = 0; l < 63; l++)
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sum = (sum + buffer[l]) & 0xff;
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if (sum == buffer[63])
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valid = 1;
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else
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printf("Invalid checksum in EEPROM %02x %02x\n",
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sum, buffer[63]);
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}
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if (valid == 0) {
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memcpy(buffer, (void *)&default_spd_eeprom, len);
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sum = 0;
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for (l = 0; l < 63; l++)
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sum = (sum + buffer[l]) & 0xff;
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if (sum != buffer[63])
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printf("Invalid checksum in FLASH %02x %02x\n",
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sum, buffer[63]);
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buffer[63] = sum;
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}
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i2c_set_bus_num(old_bus);
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return 0;
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}
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