Shiraz Hashim f28e5c946d SPEAr: Correct SoC ID offset in misc configuration space ... SoC Core ID offset is 0x30 in miscellaneous configuration address space. It was wrongly mentioned as periph2 clk enable. Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com> Signed-off-by: Amit Virdi <amit.virdi@st.com> Acked-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>		2012-07-07 14:07:42 +02:00
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cpu	SPEAr: explicitly select clk src for UART	2012-07-07 14:07:42 +02:00
dts	tegra: fdt: Add keyboard controller definition	2012-05-15 08:31:40 +02:00
include/asm	SPEAr: Correct SoC ID offset in misc configuration space	2012-07-07 14:07:42 +02:00
lib	net: move bootfile init into eth_initialize	2012-05-15 17:32:33 -05:00
config.mk	Makefile: Add a 'checkthumb' rule	2012-05-15 08:31:26 +02:00