mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-06 13:14:27 +00:00
41575d8e4c
This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
173 lines
4.8 KiB
C
173 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Copyright (c) 2020 Sartura Ltd.
|
|
*
|
|
* Author: Robert Marko <robert.marko@sartura.hr>
|
|
*
|
|
* Based on Linux driver
|
|
*/
|
|
|
|
#include <asm/io.h>
|
|
#include <common.h>
|
|
#include <dm.h>
|
|
#include <dt-bindings/reset/qcom,ipq4019-reset.h>
|
|
#include <reset-uclass.h>
|
|
#include <linux/bitops.h>
|
|
#include <malloc.h>
|
|
|
|
struct ipq4019_reset_priv {
|
|
phys_addr_t base;
|
|
};
|
|
|
|
struct qcom_reset_map {
|
|
unsigned int reg;
|
|
u8 bit;
|
|
};
|
|
|
|
static const struct qcom_reset_map gcc_ipq4019_resets[] = {
|
|
[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
|
|
[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
|
|
[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
|
|
[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
|
|
[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
|
|
[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
|
|
[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
|
|
[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
|
|
[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
|
|
[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
|
|
[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
|
|
[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
|
|
[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
|
|
[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
|
|
[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
|
|
[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
|
|
[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
|
|
[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
|
|
[PCIE_AHB_ARES] = { 0x1d010, 10 },
|
|
[PCIE_PWR_ARES] = { 0x1d010, 9 },
|
|
[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
|
|
[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
|
|
[PCIE_PHY_ARES] = { 0x1d010, 6 },
|
|
[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
|
|
[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
|
|
[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
|
|
[PCIE_PIPE_ARES] = { 0x1d010, 2 },
|
|
[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
|
|
[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
|
|
[ESS_RESET] = { 0x12008, 0},
|
|
[GCC_BLSP1_BCR] = {0x01000, 0},
|
|
[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
|
|
[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
|
|
[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
|
|
[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
|
|
[GCC_BIMC_BCR] = {0x04000, 0},
|
|
[GCC_TLMM_BCR] = {0x05000, 0},
|
|
[GCC_IMEM_BCR] = {0x0E000, 0},
|
|
[GCC_ESS_BCR] = {0x12008, 0},
|
|
[GCC_PRNG_BCR] = {0x13000, 0},
|
|
[GCC_BOOT_ROM_BCR] = {0x13008, 0},
|
|
[GCC_CRYPTO_BCR] = {0x16000, 0},
|
|
[GCC_SDCC1_BCR] = {0x18000, 0},
|
|
[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
|
|
[GCC_AUDIO_BCR] = {0x1B008, 0},
|
|
[GCC_QPIC_BCR] = {0x1C000, 0},
|
|
[GCC_PCIE_BCR] = {0x1D000, 0},
|
|
[GCC_USB2_BCR] = {0x1E008, 0},
|
|
[GCC_USB2_PHY_BCR] = {0x1E018, 0},
|
|
[GCC_USB3_BCR] = {0x1E024, 0},
|
|
[GCC_USB3_PHY_BCR] = {0x1E034, 0},
|
|
[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
|
|
[GCC_PCNOC_BCR] = {0x2102C, 0},
|
|
[GCC_DCD_BCR] = {0x21038, 0},
|
|
[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
|
|
[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
|
|
[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
|
|
[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
|
|
[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
|
|
[GCC_TCSR_BCR] = {0x22000, 0},
|
|
[GCC_MPM_BCR] = {0x24000, 0},
|
|
[GCC_SPDM_BCR] = {0x25000, 0},
|
|
};
|
|
|
|
static int ipq4019_reset_assert(struct reset_ctl *rst)
|
|
{
|
|
struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
|
|
const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
|
|
const struct qcom_reset_map *map;
|
|
u32 value;
|
|
|
|
map = &reset_map[rst->id];
|
|
|
|
value = readl(priv->base + map->reg);
|
|
value |= BIT(map->bit);
|
|
writel(value, priv->base + map->reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ipq4019_reset_deassert(struct reset_ctl *rst)
|
|
{
|
|
struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
|
|
const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
|
|
const struct qcom_reset_map *map;
|
|
u32 value;
|
|
|
|
map = &reset_map[rst->id];
|
|
|
|
value = readl(priv->base + map->reg);
|
|
value &= ~BIT(map->bit);
|
|
writel(value, priv->base + map->reg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int ipq4019_reset_free(struct reset_ctl *rst)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int ipq4019_reset_request(struct reset_ctl *rst)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct reset_ops ipq4019_reset_ops = {
|
|
.request = ipq4019_reset_request,
|
|
.rfree = ipq4019_reset_free,
|
|
.rst_assert = ipq4019_reset_assert,
|
|
.rst_deassert = ipq4019_reset_deassert,
|
|
};
|
|
|
|
static const struct udevice_id ipq4019_reset_ids[] = {
|
|
{ .compatible = "qcom,gcc-reset-ipq4019" },
|
|
{ }
|
|
};
|
|
|
|
static int ipq4019_reset_probe(struct udevice *dev)
|
|
{
|
|
struct ipq4019_reset_priv *priv = dev_get_priv(dev);
|
|
|
|
priv->base = dev_read_addr(dev);
|
|
if (priv->base == FDT_ADDR_T_NONE)
|
|
return -EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_DRIVER(ipq4019_reset) = {
|
|
.name = "ipq4019_reset",
|
|
.id = UCLASS_RESET,
|
|
.of_match = ipq4019_reset_ids,
|
|
.ops = &ipq4019_reset_ops,
|
|
.probe = ipq4019_reset_probe,
|
|
.priv_auto = sizeof(struct ipq4019_reset_priv),
|
|
};
|