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8a8f084e4f
This patch is added to support SPL feature on AM335X platform. In this patch, MMC1 is configured as boot device for SPL and support for other devices will be added in the next patch series. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Tom Rini <trini@ti.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
201 lines
5.1 KiB
C
201 lines
5.1 KiB
C
/*
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* emif4.c
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*
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* AM33XX emif4 configuration file
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct ddr_regs *ddrregs = (struct ddr_regs *)DDR_PHY_BASE_ADDR;
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struct vtp_reg *vtpreg = (struct vtp_reg *)VTP0_CTRL_ADDR;
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struct ddr_ctrl *ddrctrl = (struct ddr_ctrl *)DDR_CTRL_ADDR;
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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gd->ram_size = get_ram_size(
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(void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_MAX_RAM_BANK_SIZE);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = gd->ram_size;
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}
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#ifdef CONFIG_SPL_BUILD
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static void data_macro_config(int dataMacroNum)
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{
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struct ddr_data data;
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data.datardsratio0 = ((DDR2_RD_DQS<<30)|(DDR2_RD_DQS<<20)
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|(DDR2_RD_DQS<<10)|(DDR2_RD_DQS<<0));
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data.datardsratio1 = DDR2_RD_DQS>>2;
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data.datawdsratio0 = ((DDR2_WR_DQS<<30)|(DDR2_WR_DQS<<20)
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|(DDR2_WR_DQS<<10)|(DDR2_WR_DQS<<0));
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data.datawdsratio1 = DDR2_WR_DQS>>2;
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data.datawiratio0 = ((DDR2_PHY_WRLVL<<30)|(DDR2_PHY_WRLVL<<20)
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|(DDR2_PHY_WRLVL<<10)|(DDR2_PHY_WRLVL<<0));
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data.datawiratio1 = DDR2_PHY_WRLVL>>2;
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data.datagiratio0 = ((DDR2_PHY_GATELVL<<30)|(DDR2_PHY_GATELVL<<20)
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|(DDR2_PHY_GATELVL<<10)|(DDR2_PHY_GATELVL<<0));
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data.datagiratio1 = DDR2_PHY_GATELVL>>2;
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data.datafwsratio0 = ((DDR2_PHY_FIFO_WE<<30)|(DDR2_PHY_FIFO_WE<<20)
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|(DDR2_PHY_FIFO_WE<<10)|(DDR2_PHY_FIFO_WE<<0));
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data.datafwsratio1 = DDR2_PHY_FIFO_WE>>2;
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data.datawrsratio0 = ((DDR2_PHY_WR_DATA<<30)|(DDR2_PHY_WR_DATA<<20)
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|(DDR2_PHY_WR_DATA<<10)|(DDR2_PHY_WR_DATA<<0));
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data.datawrsratio1 = DDR2_PHY_WR_DATA>>2;
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data.datadldiff0 = PHY_DLL_LOCK_DIFF;
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config_ddr_data(dataMacroNum, &data);
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}
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static void cmd_macro_config(void)
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{
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struct cmd_control cmd;
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cmd.cmd0csratio = DDR2_RATIO;
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cmd.cmd0csforce = CMD_FORCE;
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cmd.cmd0csdelay = CMD_DELAY;
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cmd.cmd0dldiff = DDR2_DLL_LOCK_DIFF;
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cmd.cmd0iclkout = DDR2_INVERT_CLKOUT;
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cmd.cmd1csratio = DDR2_RATIO;
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cmd.cmd1csforce = CMD_FORCE;
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cmd.cmd1csdelay = CMD_DELAY;
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cmd.cmd1dldiff = DDR2_DLL_LOCK_DIFF;
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cmd.cmd1iclkout = DDR2_INVERT_CLKOUT;
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cmd.cmd2csratio = DDR2_RATIO;
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cmd.cmd2csforce = CMD_FORCE;
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cmd.cmd2csdelay = CMD_DELAY;
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cmd.cmd2dldiff = DDR2_DLL_LOCK_DIFF;
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cmd.cmd2iclkout = DDR2_INVERT_CLKOUT;
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config_cmd_ctrl(&cmd);
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}
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static void config_vtp(void)
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{
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writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_ENABLE,
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&vtpreg->vtp0ctrlreg);
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writel(readl(&vtpreg->vtp0ctrlreg) & (~VTP_CTRL_START_EN),
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&vtpreg->vtp0ctrlreg);
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writel(readl(&vtpreg->vtp0ctrlreg) | VTP_CTRL_START_EN,
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&vtpreg->vtp0ctrlreg);
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/* Poll for READY */
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while ((readl(&vtpreg->vtp0ctrlreg) & VTP_CTRL_READY) !=
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VTP_CTRL_READY)
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;
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}
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static void config_emif_ddr2(void)
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{
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int i;
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int ret;
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struct sdram_config cfg;
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struct sdram_timing tmg;
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struct ddr_phy_control phyc;
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/*Program EMIF0 CFG Registers*/
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phyc.reg = EMIF_READ_LATENCY;
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phyc.reg_sh = EMIF_READ_LATENCY;
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phyc.reg2 = EMIF_READ_LATENCY;
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tmg.time1 = EMIF_TIM1;
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tmg.time1_sh = EMIF_TIM1;
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tmg.time2 = EMIF_TIM2;
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tmg.time2_sh = EMIF_TIM2;
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tmg.time3 = EMIF_TIM3;
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tmg.time3_sh = EMIF_TIM3;
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cfg.sdrcr = EMIF_SDCFG;
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cfg.sdrcr2 = EMIF_SDCFG;
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cfg.refresh = 0x00004650;
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cfg.refresh_sh = 0x00004650;
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/* Program EMIF instance */
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ret = config_ddr_phy(&phyc);
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if (ret < 0)
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printf("Couldn't configure phyc\n");
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ret = config_sdram(&cfg);
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if (ret < 0)
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printf("Couldn't configure SDRAM\n");
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ret = set_sdram_timings(&tmg);
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if (ret < 0)
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printf("Couldn't configure timings\n");
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/* Delay */
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for (i = 0; i < 5000; i++)
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;
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cfg.refresh = EMIF_SDREF;
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cfg.refresh_sh = EMIF_SDREF;
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cfg.sdrcr = EMIF_SDCFG;
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cfg.sdrcr2 = EMIF_SDCFG;
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ret = config_sdram(&cfg);
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if (ret < 0)
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printf("Couldn't configure SDRAM\n");
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}
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void config_ddr(void)
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{
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int data_macro_0 = 0;
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int data_macro_1 = 1;
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struct ddr_ioctrl ioctrl;
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enable_emif_clocks();
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config_vtp();
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cmd_macro_config();
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data_macro_config(data_macro_0);
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data_macro_config(data_macro_1);
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writel(PHY_RANK0_DELAY, &ddrregs->dt0rdelays0);
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writel(PHY_RANK0_DELAY, &ddrregs->dt1rdelays0);
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ioctrl.cmd1ctl = DDR_IOCTRL_VALUE;
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ioctrl.cmd2ctl = DDR_IOCTRL_VALUE;
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ioctrl.cmd3ctl = DDR_IOCTRL_VALUE;
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ioctrl.data1ctl = DDR_IOCTRL_VALUE;
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ioctrl.data2ctl = DDR_IOCTRL_VALUE;
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config_io_ctrl(&ioctrl);
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writel(readl(&ddrctrl->ddrioctrl) & 0xefffffff, &ddrctrl->ddrioctrl);
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writel(readl(&ddrctrl->ddrckectrl) | 0x00000001, &ddrctrl->ddrckectrl);
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config_emif_ddr2();
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}
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#endif
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