mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-01 17:10:11 +00:00
c79cbb5952
If for some reason, TSC timer frequency cannot be determined from hardware, nor is it specified in the device tree, U-Boot will panic resulting in endless reset during boot. Let's define a default TSC timer frequency using the Kconfig value CONFIG_X86_TSC_TIMER_FREQ (note: #include must be used instead of /include/ otherwise the macro is not pre-processed). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
75 lines
1.3 KiB
Text
75 lines
1.3 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include <dt-bindings/interrupt-router/intel-irq.h>
|
|
|
|
/include/ "skeleton.dtsi"
|
|
/include/ "serial.dtsi"
|
|
/include/ "keyboard.dtsi"
|
|
/include/ "reset.dtsi"
|
|
/include/ "rtc.dtsi"
|
|
|
|
#include "tsc_timer.dtsi"
|
|
#include "smbios.dtsi"
|
|
|
|
/ {
|
|
model = "QEMU x86 (I440FX)";
|
|
compatible = "qemu,x86";
|
|
|
|
config {
|
|
silent_console = <0>;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "/serial";
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
cpu@0 {
|
|
device_type = "cpu";
|
|
compatible = "cpu-qemu";
|
|
u-boot,dm-pre-reloc;
|
|
reg = <0>;
|
|
intel,apic-id = <0>;
|
|
};
|
|
};
|
|
|
|
pci {
|
|
compatible = "pci-x86";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
u-boot,dm-pre-reloc;
|
|
ranges = <0x02000000 0x0 0xc0000000 0xc0000000 0 0x10000000
|
|
0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
|
|
0x01000000 0x0 0x2000 0x2000 0 0xe000>;
|
|
|
|
pch@1,0 {
|
|
reg = <0x00000800 0 0 0 0>;
|
|
compatible = "intel,pch7";
|
|
u-boot,dm-pre-reloc;
|
|
|
|
irq-router {
|
|
compatible = "intel,irq-router";
|
|
u-boot,dm-pre-reloc;
|
|
intel,pirq-config = "pci";
|
|
intel,pirq-link = <0x60 4>;
|
|
intel,pirq-mask = <0x0e40>;
|
|
intel,pirq-routing = <
|
|
/* PIIX UHCI */
|
|
PCI_BDF(0, 1, 2) INTD PIRQD
|
|
/* e1000 NIC */
|
|
PCI_BDF(0, 3, 0) INTA PIRQC
|
|
>;
|
|
};
|
|
};
|
|
};
|
|
|
|
};
|