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https://github.com/AsahiLinux/u-boot
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d7e8ac6f45
Added the AFE (Analog Front End) settings for stability to the Broadcom Cygnus phy. This improves the time take to perform auto negotiation. Signed-off-by: Arun Parameswaran <arun.parameswaran@broadcom.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
375 lines
9.5 KiB
C
375 lines
9.5 KiB
C
/*
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* Broadcom PHY drivers
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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* author Andy Fleming
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*/
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#include <config.h>
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#include <common.h>
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#include <phy.h>
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/* Broadcom BCM54xx -- taken from linux sungem_phy */
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#define MIIM_BCM54xx_AUXCNTL 0x18
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#define MIIM_BCM54xx_AUXCNTL_ENCODE(val) (((val & 0x7) << 12)|(val & 0x7))
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#define MIIM_BCM54xx_AUXSTATUS 0x19
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#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK 0x0700
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#define MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT 8
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#define MIIM_BCM54XX_SHD 0x1c
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#define MIIM_BCM54XX_SHD_WRITE 0x8000
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#define MIIM_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10)
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#define MIIM_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
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#define MIIM_BCM54XX_SHD_WR_ENCODE(val, data) \
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(MIIM_BCM54XX_SHD_WRITE | MIIM_BCM54XX_SHD_VAL(val) | \
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MIIM_BCM54XX_SHD_DATA(data))
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#define MIIM_BCM54XX_EXP_DATA 0x15 /* Expansion register data */
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#define MIIM_BCM54XX_EXP_SEL 0x17 /* Expansion register select */
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#define MIIM_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */
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#define MIIM_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */
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#define MIIM_BCM_AUXCNTL_SHDWSEL_MISC 0x0007
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#define MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN 0x0800
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#define MIIM_BCM_CHANNEL_WIDTH 0x2000
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static void bcm_phy_write_misc(struct phy_device *phydev,
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u16 reg, u16 chl, u16 value)
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{
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int reg_val;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL,
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MIIM_BCM_AUXCNTL_SHDWSEL_MISC);
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reg_val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL);
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reg_val |= MIIM_BCM_AUXCNTL_ACTL_SMDSP_EN;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg_val);
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reg_val = (chl * MIIM_BCM_CHANNEL_WIDTH) | reg;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL, reg_val);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA, value);
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}
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/* Broadcom BCM5461S */
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static int bcm5461_config(struct phy_device *phydev)
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{
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genphy_config_aneg(phydev);
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phy_reset(phydev);
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return 0;
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}
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static int bcm54xx_parse_status(struct phy_device *phydev)
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{
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unsigned int mii_reg;
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mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXSTATUS);
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switch ((mii_reg & MIIM_BCM54xx_AUXSTATUS_LINKMODE_MASK) >>
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MIIM_BCM54xx_AUXSTATUS_LINKMODE_SHIFT) {
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case 1:
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phydev->duplex = DUPLEX_HALF;
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phydev->speed = SPEED_10;
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break;
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case 2:
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phydev->duplex = DUPLEX_FULL;
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phydev->speed = SPEED_10;
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break;
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case 3:
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phydev->duplex = DUPLEX_HALF;
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phydev->speed = SPEED_100;
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break;
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case 5:
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phydev->duplex = DUPLEX_FULL;
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phydev->speed = SPEED_100;
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break;
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case 6:
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phydev->duplex = DUPLEX_HALF;
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phydev->speed = SPEED_1000;
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break;
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case 7:
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phydev->duplex = DUPLEX_FULL;
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phydev->speed = SPEED_1000;
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break;
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default:
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printf("Auto-neg error, defaulting to 10BT/HD\n");
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phydev->duplex = DUPLEX_HALF;
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phydev->speed = SPEED_10;
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break;
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}
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return 0;
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}
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static int bcm54xx_startup(struct phy_device *phydev)
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{
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int ret;
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/* Read the Status (2x to make sure link is right) */
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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return bcm54xx_parse_status(phydev);
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}
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/* Broadcom BCM5482S */
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/*
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* "Ethernet@Wirespeed" needs to be enabled to achieve link in certain
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* circumstances. eg a gigabit TSEC connected to a gigabit switch with
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* a 4-wire ethernet cable. Both ends advertise gigabit, but can't
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* link. "Ethernet@Wirespeed" reduces advertised speed until link
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* can be achieved.
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*/
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static u32 bcm5482_read_wirespeed(struct phy_device *phydev, u32 reg)
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{
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return (phy_read(phydev, MDIO_DEVAD_NONE, reg) & 0x8FFF) | 0x8010;
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}
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static int bcm5482_config(struct phy_device *phydev)
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{
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unsigned int reg;
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/* reset the PHY */
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reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
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reg |= BMCR_RESET;
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phy_write(phydev, MDIO_DEVAD_NONE, MII_BMCR, reg);
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/* Setup read from auxilary control shadow register 7 */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL,
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MIIM_BCM54xx_AUXCNTL_ENCODE(7));
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/* Read Misc Control register and or in Ethernet@Wirespeed */
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reg = bcm5482_read_wirespeed(phydev, MIIM_BCM54xx_AUXCNTL);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, reg);
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/* Initial config/enable of secondary SerDes interface */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD,
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MIIM_BCM54XX_SHD_WR_ENCODE(0x14, 0xf));
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/* Write intial value to secondary SerDes Contol */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
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MIIM_BCM54XX_EXP_SEL_SSD | 0);
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA,
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BMCR_ANRESTART);
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/* Enable copper/fiber auto-detect */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_SHD,
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MIIM_BCM54XX_SHD_WR_ENCODE(0x1e, 0x201));
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genphy_config_aneg(phydev);
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return 0;
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}
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static int bcm_cygnus_startup(struct phy_device *phydev)
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{
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int ret;
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/* Read the Status (2x to make sure link is right) */
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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return genphy_parse_link(phydev);
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}
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static void bcm_cygnus_afe(struct phy_device *phydev)
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{
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/* ensures smdspclk is enabled */
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54xx_AUXCNTL, 0x0c30);
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/* AFE_VDAC_ICTRL_0 bit 7:4 Iq=1100 for 1g 10bt, normal modes */
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bcm_phy_write_misc(phydev, 0x39, 0x01, 0xA7C8);
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/* AFE_HPF_TRIM_OTHERS bit11=1, short cascode for all modes*/
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bcm_phy_write_misc(phydev, 0x3A, 0x00, 0x0803);
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/* AFE_TX_CONFIG_1 bit 7:4 Iq=1100 for test modes */
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bcm_phy_write_misc(phydev, 0x3A, 0x01, 0xA740);
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/* AFE TEMPSEN_OTHERS rcal_HT, rcal_LT 10000 */
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bcm_phy_write_misc(phydev, 0x3A, 0x03, 0x8400);
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/* AFE_FUTURE_RSV bit 2:0 rccal <2:0>=100 */
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bcm_phy_write_misc(phydev, 0x3B, 0x00, 0x0004);
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/* Adjust bias current trim to overcome digital offSet */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x02);
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/* make rcal=100, since rdb default is 000 */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B1);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010);
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/* CORE_EXPB0, Reset R_CAL/RC_CAL Engine */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0010);
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/* CORE_EXPB0, Disable Reset R_CAL/RC_CAL Engine */
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phy_write(phydev, MDIO_DEVAD_NONE, 0x17, 0x00B0);
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phy_write(phydev, MDIO_DEVAD_NONE, 0x15, 0x0000);
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}
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static int bcm_cygnus_config(struct phy_device *phydev)
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{
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genphy_config_aneg(phydev);
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phy_reset(phydev);
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/* AFE settings for PHY stability */
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bcm_cygnus_afe(phydev);
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/* Forcing aneg after applying the AFE settings */
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genphy_restart_aneg(phydev);
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return 0;
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}
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/*
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* Find out if PHY is in copper or serdes mode by looking at Expansion Reg
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* 0x42 - "Operating Mode Status Register"
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*/
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static int bcm5482_is_serdes(struct phy_device *phydev)
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{
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u16 val;
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int serdes = 0;
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
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MIIM_BCM54XX_EXP_SEL_ER | 0x42);
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA);
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switch (val & 0x1f) {
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case 0x0d: /* RGMII-to-100Base-FX */
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case 0x0e: /* RGMII-to-SGMII */
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case 0x0f: /* RGMII-to-SerDes */
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case 0x12: /* SGMII-to-SerDes */
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case 0x13: /* SGMII-to-100Base-FX */
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case 0x16: /* SerDes-to-Serdes */
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serdes = 1;
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break;
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case 0x6: /* RGMII-to-Copper */
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case 0x14: /* SGMII-to-Copper */
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case 0x17: /* SerDes-to-Copper */
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break;
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default:
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printf("ERROR, invalid PHY mode (0x%x\n)", val);
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break;
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}
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return serdes;
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}
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/*
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* Determine SerDes link speed and duplex from Expansion reg 0x42 "Operating
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* Mode Status Register"
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*/
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static u32 bcm5482_parse_serdes_sr(struct phy_device *phydev)
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{
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u16 val;
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int i = 0;
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/* Wait 1s for link - Clause 37 autonegotiation happens very fast */
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while (1) {
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phy_write(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_SEL,
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MIIM_BCM54XX_EXP_SEL_ER | 0x42);
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val = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_BCM54XX_EXP_DATA);
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if (val & 0x8000)
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break;
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if (i++ > 1000) {
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phydev->link = 0;
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return 1;
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}
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udelay(1000); /* 1 ms */
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}
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phydev->link = 1;
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switch ((val >> 13) & 0x3) {
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case (0x00):
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phydev->speed = 10;
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break;
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case (0x01):
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phydev->speed = 100;
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break;
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case (0x02):
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phydev->speed = 1000;
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break;
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}
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phydev->duplex = (val & 0x1000) == 0x1000;
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return 0;
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}
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/*
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* Figure out if BCM5482 is in serdes or copper mode and determine link
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* configuration accordingly
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*/
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static int bcm5482_startup(struct phy_device *phydev)
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{
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int ret;
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if (bcm5482_is_serdes(phydev)) {
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bcm5482_parse_serdes_sr(phydev);
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phydev->port = PORT_FIBRE;
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return 0;
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}
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/* Wait for auto-negotiation to complete or fail */
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ret = genphy_update_link(phydev);
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if (ret)
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return ret;
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/* Parse BCM54xx copper aux status register */
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return bcm54xx_parse_status(phydev);
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}
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static struct phy_driver BCM5461S_driver = {
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.name = "Broadcom BCM5461S",
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.uid = 0x2060c0,
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.mask = 0xfffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &bcm5461_config,
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.startup = &bcm54xx_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver BCM5464S_driver = {
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.name = "Broadcom BCM5464S",
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.uid = 0x2060b0,
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.mask = 0xfffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &bcm5461_config,
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.startup = &bcm54xx_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver BCM5482S_driver = {
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.name = "Broadcom BCM5482S",
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.uid = 0x143bcb0,
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.mask = 0xffffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &bcm5482_config,
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.startup = &bcm5482_startup,
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.shutdown = &genphy_shutdown,
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};
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static struct phy_driver BCM_CYGNUS_driver = {
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.name = "Broadcom CYGNUS GPHY",
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.uid = 0xae025200,
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.mask = 0xfffff0,
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.features = PHY_GBIT_FEATURES,
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.config = &bcm_cygnus_config,
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.startup = &bcm_cygnus_startup,
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.shutdown = &genphy_shutdown,
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};
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int phy_broadcom_init(void)
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{
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phy_register(&BCM5482S_driver);
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phy_register(&BCM5464S_driver);
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phy_register(&BCM5461S_driver);
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phy_register(&BCM_CYGNUS_driver);
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return 0;
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}
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