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6ecaee8201
There is no need to set the VBUS power enable to 0 first and then to 1. Set it to 1 in the gpio_direction_output() function. While at it, use the standard naming convention for the GPIO comment. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
453 lines
13 KiB
C
453 lines
13 KiB
C
/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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* Jason Liu <r64343@freescale.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx5x_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/clock.h>
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#include <asm/errno.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <asm/gpio.h>
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#include <pmic.h>
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#include <dialog_pmic.h>
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#include <fsl_pmic.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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u32 size1, size2;
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size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
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gd->ram_size = size1 + size2;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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}
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u32 get_board_rev(void)
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{
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struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
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struct fuse_bank *bank = &iim->bank[0];
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struct fuse_bank0_regs *fuse =
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(struct fuse_bank0_regs *)bank->fuse_regs;
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int rev = readl(&fuse->gp[6]);
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return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
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}
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static void setup_iomux_uart(void)
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{
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/* UART1 RXD */
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mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
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/* UART1 TXD */
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mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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}
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#ifdef CONFIG_USB_EHCI_MX5
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int board_ehci_hcd_init(int port)
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{
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/* request VBUS power enable pin, GPIO7_8 */
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mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
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gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
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return 0;
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}
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#endif
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static void setup_iomux_fec(void)
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{
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/*FEC_MDIO*/
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mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
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mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
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/*FEC_MDC*/
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mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
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/* FEC RXD1 */
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mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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/* FEC RXD0 */
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mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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/* FEC TXD1 */
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mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
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/* FEC TXD0 */
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mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
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/* FEC TX_EN */
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mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
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/* FEC TX_CLK */
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mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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/* FEC RX_ER */
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mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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/* FEC CRS */
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mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
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PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR, 1},
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{MMC_SDHC3_BASE_ADDR, 1},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret;
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mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
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gpio_direction_input(75);
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mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
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gpio_direction_input(77);
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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ret = !gpio_get_value(77); /* GPIO3_13 */
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else
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ret = !gpio_get_value(75); /* GPIO3_11 */
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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u32 index;
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s32 status = 0;
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
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switch (index) {
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case 0:
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mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA0,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA1,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA2,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA3,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_EIM_DA13,
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IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_DRV_HIGH);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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break;
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case 1:
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mxc_request_iomux(MX53_PIN_ATA_RESET_B,
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IOMUX_CONFIG_ALT2);
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mxc_request_iomux(MX53_PIN_ATA_IORDY,
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IOMUX_CONFIG_ALT2);
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mxc_request_iomux(MX53_PIN_ATA_DATA8,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA9,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA10,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA11,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA0,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA1,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA2,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_ATA_DATA3,
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IOMUX_CONFIG_ALT4);
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mxc_request_iomux(MX53_PIN_EIM_DA11,
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IOMUX_CONFIG_ALT1);
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mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
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PAD_CTL_DRV_HIGH);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
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break;
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default:
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printf("Warning: you configured more ESDHC controller"
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"(%d) as supported by the board(2)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return status;
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}
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status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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}
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return status;
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}
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#endif
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static void setup_iomux_i2c(void)
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{
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/* I2C1 SDA */
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mxc_request_iomux(MX53_PIN_CSI0_D8,
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IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
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mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT,
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INPUT_CTL_PATH0);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D8,
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PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
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PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
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PAD_CTL_PUE_PULL |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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/* I2C1 SCL */
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mxc_request_iomux(MX53_PIN_CSI0_D9,
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IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION);
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mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT,
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INPUT_CTL_PATH0);
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mxc_iomux_set_pad(MX53_PIN_CSI0_D9,
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PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH |
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PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE |
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PAD_CTL_PUE_PULL |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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}
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static int power_init(void)
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{
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unsigned int val;
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int ret = -1;
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struct pmic *p;
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if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) {
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pmic_dialog_init();
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p = get_pmic();
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/* Set VDDA to 1.25V */
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val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V;
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ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val);
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ret |= pmic_reg_read(p, DA9053_SUPPLY_REG, &val);
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val |= DA9052_SUPPLY_VBCOREGO;
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ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, val);
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/* Set Vcc peripheral to 1.30V */
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ret |= pmic_reg_write(p, DA9053_BUCKPRO_REG, 0x62);
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ret |= pmic_reg_write(p, DA9053_SUPPLY_REG, 0x62);
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}
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if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) {
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pmic_init();
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p = get_pmic();
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/* Set VDDGP to 1.25V for 1GHz on SW1 */
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pmic_reg_read(p, REG_SW_0, &val);
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val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_250V_MC34708;
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ret = pmic_reg_write(p, REG_SW_0, val);
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/* Set VCC as 1.30V on SW2 */
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pmic_reg_read(p, REG_SW_1, &val);
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val = (val & ~SWx_VOLT_MASK_MC34708) | SWx_1_300V_MC34708;
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ret |= pmic_reg_write(p, REG_SW_1, val);
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/* Set global reset timer to 4s */
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pmic_reg_read(p, REG_POWER_CTL2, &val);
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val = (val & ~TIMER_MASK_MC34708) | TIMER_4S_MC34708;
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ret |= pmic_reg_write(p, REG_POWER_CTL2, val);
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/* Set VUSBSEL and VUSBEN for USB PHY supply*/
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pmic_reg_read(p, REG_MODE_0, &val);
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val |= (VUSBSEL_MC34708 | VUSBEN_MC34708);
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ret |= pmic_reg_write(p, REG_MODE_0, val);
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/* Set SWBST to 5V in auto mode */
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val = SWBST_AUTO;
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ret |= pmic_reg_write(p, SWBST_CTRL, val);
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}
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return ret;
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}
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static void clock_1GHz(void)
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{
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int ret;
|
|
u32 ref_clk = CONFIG_SYS_MX5_HCLK;
|
|
/*
|
|
* After increasing voltage to 1.25V, we can switch
|
|
* CPU clock to 1GHz and DDR to 400MHz safely
|
|
*/
|
|
ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
|
|
if (ret)
|
|
printf("CPU: Switch CPU clock to 1GHZ failed\n");
|
|
|
|
ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
|
|
ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
|
|
if (ret)
|
|
printf("CPU: Switch DDR clock to 400MHz failed\n");
|
|
}
|
|
|
|
int board_early_init_f(void)
|
|
{
|
|
setup_iomux_uart();
|
|
setup_iomux_fec();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int print_cpuinfo(void)
|
|
{
|
|
u32 cpurev;
|
|
|
|
cpurev = get_cpu_rev();
|
|
printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n",
|
|
(cpurev & 0xFF000) >> 12,
|
|
(cpurev & 0x000F0) >> 4,
|
|
(cpurev & 0x0000F) >> 0,
|
|
mxc_get_clock(MXC_ARM_CLK) / 1000000);
|
|
printf("Reset cause: %s\n", get_reset_cause());
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_BOARD_LATE_INIT
|
|
int board_late_init(void)
|
|
{
|
|
setup_iomux_i2c();
|
|
if (!power_init())
|
|
clock_1GHz();
|
|
print_cpuinfo();
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
int board_init(void)
|
|
{
|
|
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
|
|
|
|
mxc_set_sata_internal_clock();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: MX53 LOCO\n");
|
|
|
|
return 0;
|
|
}
|