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https://github.com/AsahiLinux/u-boot
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f1a225229a
RK3308 is a quad Cortex A35 based SOC with rich audio interfaces(I2S/PCM/TDM/PDM/SPDIF/VAD/HDMI ARC), which designed for intelligent voice interaction and audio input/output processing. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
290 lines
7.2 KiB
C
290 lines
7.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2018 Rockchip Electronics Co., Ltd.
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*/
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#ifndef _ASM_ARCH_CRU_RK3308_H
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#define _ASM_ARCH_CRU_RK3308_H
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#include <common.h>
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#define MHz 1000000
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#define OSC_HZ (24 * MHz)
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#define APLL_HZ (816 * MHz)
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#define CORE_ACLK_HZ 408000000
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#define CORE_DBG_HZ 204000000
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#define BUS_ACLK_HZ 200000000
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#define BUS_HCLK_HZ 100000000
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#define BUS_PCLK_HZ 100000000
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#define PERI_ACLK_HZ 200000000
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#define PERI_HCLK_HZ 100000000
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#define PERI_PCLK_HZ 100000000
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#define AUDIO_HCLK_HZ 100000000
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#define AUDIO_PCLK_HZ 100000000
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#define RK3308_PLL_CON(x) ((x) * 0x4)
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#define RK3308_MODE_CON 0xa0
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/* RK3308 pll id */
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enum rk3308_pll_id {
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APLL,
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DPLL,
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VPLL0,
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VPLL1,
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PLL_COUNT,
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};
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struct rk3308_clk_info {
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unsigned long id;
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char *name;
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};
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/* Private data for the clock driver - used by rockchip_get_cru() */
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struct rk3308_clk_priv {
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struct rk3308_cru *cru;
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ulong armclk_hz;
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ulong dpll_hz;
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ulong vpll0_hz;
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ulong vpll1_hz;
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};
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struct rk3308_cru {
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struct rk3308_pll {
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unsigned int con0;
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unsigned int con1;
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unsigned int con2;
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unsigned int con3;
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unsigned int con4;
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unsigned int reserved0[3];
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} pll[4];
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unsigned int reserved1[8];
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unsigned int mode;
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unsigned int misc;
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unsigned int reserved2[2];
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unsigned int glb_cnt_th;
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unsigned int glb_rst_st;
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unsigned int glb_srst_fst;
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unsigned int glb_srst_snd;
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unsigned int glb_rst_con;
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unsigned int pll_lock;
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unsigned int reserved3[6];
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unsigned int hwffc_con0;
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unsigned int reserved4;
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unsigned int hwffc_th;
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unsigned int hwffc_intst;
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unsigned int apll_con0_s;
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unsigned int apll_con1_s;
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unsigned int clksel_con0_s;
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unsigned int reserved5;
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unsigned int clksel_con[74];
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unsigned int reserved6[54];
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unsigned int clkgate_con[15];
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unsigned int reserved7[(0x380 - 0x338) / 4 - 1];
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unsigned int ssgtbl[32];
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unsigned int softrst_con[10];
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unsigned int reserved8[(0x480 - 0x424) / 4 - 1];
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unsigned int sdmmc_con[2];
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unsigned int sdio_con[2];
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unsigned int emmc_con[2];
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};
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enum {
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/* PLLCON0*/
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PLL_BP_SHIFT = 15,
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PLL_POSTDIV1_SHIFT = 12,
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PLL_POSTDIV1_MASK = 7 << PLL_POSTDIV1_SHIFT,
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PLL_FBDIV_SHIFT = 0,
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PLL_FBDIV_MASK = 0xfff,
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/* PLLCON1 */
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PLL_PDSEL_SHIFT = 15,
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PLL_PD1_SHIFT = 14,
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PLL_PD_SHIFT = 13,
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PLL_PD_MASK = 1 << PLL_PD_SHIFT,
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PLL_DSMPD_SHIFT = 12,
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PLL_DSMPD_MASK = 1 << PLL_DSMPD_SHIFT,
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PLL_LOCK_STATUS_SHIFT = 10,
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PLL_LOCK_STATUS_MASK = 1 << PLL_LOCK_STATUS_SHIFT,
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PLL_POSTDIV2_SHIFT = 6,
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PLL_POSTDIV2_MASK = 7 << PLL_POSTDIV2_SHIFT,
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PLL_REFDIV_SHIFT = 0,
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PLL_REFDIV_MASK = 0x3f,
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/* PLLCON2 */
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PLL_FOUT4PHASEPD_SHIFT = 27,
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PLL_FOUTVCOPD_SHIFT = 26,
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PLL_FOUTPOSTDIVPD_SHIFT = 25,
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PLL_DACPD_SHIFT = 24,
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PLL_FRAC_DIV = 0xffffff,
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/* CRU_MODE */
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PLLMUX_FROM_XIN24M = 0,
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PLLMUX_FROM_PLL,
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PLLMUX_FROM_RTC32K,
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USBPHY480M_MODE_SHIFT = 8,
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USBPHY480M_MODE_MASK = 3 << USBPHY480M_MODE_SHIFT,
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VPLL1_MODE_SHIFT = 6,
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VPLL1_MODE_MASK = 3 << VPLL1_MODE_SHIFT,
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VPLL0_MODE_SHIFT = 4,
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VPLL0_MODE_MASK = 3 << VPLL0_MODE_SHIFT,
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DPLL_MODE_SHIFT = 2,
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DPLL_MODE_MASK = 3 << DPLL_MODE_SHIFT,
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APLL_MODE_SHIFT = 0,
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APLL_MODE_MASK = 3 << APLL_MODE_SHIFT,
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/* CRU_CLK_SEL0_CON */
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CORE_ACLK_DIV_SHIFT = 12,
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CORE_ACLK_DIV_MASK = 0x7 << CORE_ACLK_DIV_SHIFT,
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CORE_DBG_DIV_SHIFT = 8,
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CORE_DBG_DIV_MASK = 0xf << CORE_DBG_DIV_SHIFT,
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CORE_CLK_PLL_SEL_SHIFT = 6,
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CORE_CLK_PLL_SEL_MASK = 0x3 << CORE_CLK_PLL_SEL_SHIFT,
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CORE_CLK_PLL_SEL_APLL = 0,
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CORE_CLK_PLL_SEL_VPLL0,
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CORE_CLK_PLL_SEL_VPLL1,
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CORE_DIV_CON_SHIFT = 0,
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CORE_DIV_CON_MASK = 0x0f << CORE_DIV_CON_SHIFT,
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/* CRU_CLK_SEL5_CON */
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BUS_PLL_SEL_SHIFT = 6,
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BUS_PLL_SEL_MASK = 0x3 << BUS_PLL_SEL_SHIFT,
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BUS_PLL_SEL_DPLL = 0,
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BUS_PLL_SEL_VPLL0,
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BUS_PLL_SEL_VPLL1,
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BUS_ACLK_DIV_SHIFT = 0,
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BUS_ACLK_DIV_MASK = 0x1f << BUS_ACLK_DIV_SHIFT,
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/* CRU_CLK_SEL6_CON */
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BUS_PCLK_DIV_SHIFT = 8,
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BUS_PCLK_DIV_MASK = 0x1f << BUS_PCLK_DIV_SHIFT,
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BUS_HCLK_DIV_SHIFT = 0,
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BUS_HCLK_DIV_MASK = 0x1f << BUS_HCLK_DIV_SHIFT,
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/* CRU_CLK_SEL7_CON */
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CRYPTO_APK_SEL_SHIFT = 14,
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CRYPTO_APK_PLL_SEL_MASK = 3 << CRYPTO_APK_SEL_SHIFT,
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CRYPTO_PLL_SEL_DPLL = 0,
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CRYPTO_PLL_SEL_VPLL0,
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CRYPTO_PLL_SEL_VPLL1 = 0,
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CRYPTO_APK_DIV_SHIFT = 8,
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CRYPTO_APK_DIV_MASK = 0x1f << CRYPTO_APK_DIV_SHIFT,
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CRYPTO_PLL_SEL_SHIFT = 6,
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CRYPTO_PLL_SEL_MASK = 3 << CRYPTO_PLL_SEL_SHIFT,
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CRYPTO_DIV_SHIFT = 0,
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CRYPTO_DIV_MASK = 0x1f << CRYPTO_DIV_SHIFT,
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/* CRU_CLK_SEL8_CON */
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DCLK_VOP_SEL_SHIFT = 14,
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DCLK_VOP_SEL_MASK = 0x3 << DCLK_VOP_SEL_SHIFT,
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DCLK_VOP_SEL_DIVOUT = 0,
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DCLK_VOP_SEL_FRACOUT,
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DCLK_VOP_SEL_24M,
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DCLK_VOP_PLL_SEL_SHIFT = 10,
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DCLK_VOP_PLL_SEL_MASK = 0x3 << DCLK_VOP_PLL_SEL_SHIFT,
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DCLK_VOP_PLL_SEL_DPLL = 0,
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DCLK_VOP_PLL_SEL_VPLL0,
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DCLK_VOP_PLL_SEL_VPLL1,
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DCLK_VOP_DIV_SHIFT = 0,
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DCLK_VOP_DIV_MASK = 0xff,
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/* CRU_CLK_SEL25_CON */
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/* CRU_CLK_SEL26_CON */
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/* CRU_CLK_SEL27_CON */
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/* CRU_CLK_SEL28_CON */
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CLK_I2C_PLL_SEL_SHIFT = 14,
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CLK_I2C_PLL_SEL_MASK = 0x3 << CLK_I2C_PLL_SEL_SHIFT,
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CLK_I2C_PLL_SEL_DPLL = 0,
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CLK_I2C_PLL_SEL_VPLL0,
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CLK_I2C_PLL_SEL_24M,
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CLK_I2C_DIV_CON_SHIFT = 0,
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CLK_I2C_DIV_CON_MASK = 0x7f << CLK_I2C_DIV_CON_SHIFT,
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/* CRU_CLK_SEL29_CON */
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CLK_PWM_PLL_SEL_SHIFT = 14,
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CLK_PWM_PLL_SEL_MASK = 0x3 << CLK_PWM_PLL_SEL_SHIFT,
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CLK_PWM_PLL_SEL_DPLL = 0,
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CLK_PWM_PLL_SEL_VPLL0,
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CLK_PWM_PLL_SEL_24M,
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CLK_PWM_DIV_CON_SHIFT = 0,
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CLK_PWM_DIV_CON_MASK = 0x7f << CLK_PWM_DIV_CON_SHIFT,
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/* CRU_CLK_SEL30_CON */
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/* CRU_CLK_SEL31_CON */
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/* CRU_CLK_SEL32_CON */
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CLK_SPI_PLL_SEL_SHIFT = 14,
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CLK_SPI_PLL_SEL_MASK = 0x3 << CLK_SPI_PLL_SEL_SHIFT,
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CLK_SPI_PLL_SEL_DPLL = 0,
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CLK_SPI_PLL_SEL_VPLL0,
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CLK_SPI_PLL_SEL_24M,
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CLK_SPI_DIV_CON_SHIFT = 0,
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CLK_SPI_DIV_CON_MASK = 0x7f << CLK_SPI_DIV_CON_SHIFT,
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/* CRU_CLK_SEL34_CON */
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CLK_SARADC_DIV_CON_SHIFT = 0,
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CLK_SARADC_DIV_CON_MASK = 0x7ff << CLK_SARADC_DIV_CON_SHIFT,
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/* CRU_CLK_SEL36_CON */
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PERI_PLL_SEL_SHIFT = 6,
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PERI_PLL_SEL_MASK = 0x3 << PERI_PLL_SEL_SHIFT,
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PERI_PLL_DPLL = 0,
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PERI_PLL_VPLL0,
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PERI_PLL_VPLL1,
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PERI_ACLK_DIV_SHIFT = 0,
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PERI_ACLK_DIV_MASK = 0x1f << PERI_ACLK_DIV_SHIFT,
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/* CRU_CLK_SEL37_CON */
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PERI_PCLK_DIV_SHIFT = 8,
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PERI_PCLK_DIV_MASK = 0x1f << PERI_PCLK_DIV_SHIFT,
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PERI_HCLK_DIV_SHIFT = 0,
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PERI_HCLK_DIV_MASK = 0x1f << PERI_HCLK_DIV_SHIFT,
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/* CRU_CLKSEL41_CON */
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EMMC_CLK_SEL_SHIFT = 15,
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EMMC_CLK_SEL_MASK = 1 << EMMC_CLK_SEL_SHIFT,
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EMMC_CLK_SEL_EMMC = 0,
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EMMC_CLK_SEL_EMMC_DIV50,
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EMMC_PLL_SHIFT = 8,
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EMMC_PLL_MASK = 0x3 << EMMC_PLL_SHIFT,
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EMMC_SEL_DPLL = 0,
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EMMC_SEL_VPLL0,
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EMMC_SEL_VPLL1,
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EMMC_SEL_24M,
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EMMC_DIV_SHIFT = 0,
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EMMC_DIV_MASK = 0xff << EMMC_DIV_SHIFT,
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/* CRU_CLKSEL43_CON */
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MAC_CLK_SPEED_SEL_SHIFT = 15,
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MAC_CLK_SPEED_SEL_MASK = 1 << MAC_CLK_SPEED_SEL_SHIFT,
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MAC_CLK_SPEED_SEL_10M = 0,
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MAC_CLK_SPEED_SEL_100M,
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MAC_CLK_SOURCE_SEL_SHIFT = 14,
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MAC_CLK_SOURCE_SEL_MASK = 1 << MAC_CLK_SOURCE_SEL_SHIFT,
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MAC_CLK_SOURCE_SEL_INTERNAL = 0,
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MAC_CLK_SOURCE_SEL_EXTERNAL,
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MAC_PLL_SHIFT = 6,
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MAC_PLL_MASK = 0x3 << MAC_PLL_SHIFT,
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MAC_SEL_DPLL = 0,
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MAC_SEL_VPLL0,
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MAC_SEL_VPLL1,
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MAC_DIV_SHIFT = 0,
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MAC_DIV_MASK = 0x1f << MAC_DIV_SHIFT,
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/* CRU_CLK_SEL45_CON */
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AUDIO_PCLK_DIV_SHIFT = 8,
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AUDIO_PCLK_DIV_MASK = 0x1f << AUDIO_PCLK_DIV_SHIFT,
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AUDIO_PLL_SEL_SHIFT = 6,
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AUDIO_PLL_SEL_MASK = 0x3 << AUDIO_PLL_SEL_SHIFT,
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AUDIO_PLL_VPLL0 = 0,
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AUDIO_PLL_VPLL1,
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AUDIO_PLL_24M,
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AUDIO_HCLK_DIV_SHIFT = 0,
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AUDIO_HCLK_DIV_MASK = 0x1f << AUDIO_HCLK_DIV_SHIFT,
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};
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check_member(rk3308_cru, emmc_con[1], 0x494);
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#endif
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