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Corstone1000 is a platform from arm, which includes pre verified Corstone SSE710 sub-system that combines Cortex-A and Cortex-M processors [0]. This code adds the support for the Cortex-A35 implementation at host side, it contains also the necessary bits to support the Corstone 1000 FVP (Fixed Virtual Platform) [1] and also the FPGA MPS3 board implementation of this platform. [2] 0: https://developer.arm.com/documentation/102360/0000 1: https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps 2: https://developer.arm.com/documentation/dai0550/c/ Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
91 lines
1.8 KiB
C
91 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2022 ARM Limited
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* (C) Copyright 2022 Linaro
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* Rui Miguel Silva <rui.silva@linaro.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <netdev.h>
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#include <dm/platform_data/serial_pl01x.h>
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#include <asm/armv8/mmu.h>
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#include <asm/global_data.h>
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static struct mm_region corstone1000_mem_map[] = {
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{
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/* CVM */
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.virt = 0x02000000UL,
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.phys = 0x02000000UL,
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.size = 0x02000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* QSPI */
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.virt = 0x08000000UL,
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.phys = 0x08000000UL,
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.size = 0x08000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* Host Peripherals */
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.virt = 0x1A000000UL,
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.phys = 0x1A000000UL,
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.size = 0x26000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* USB */
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.virt = 0x40200000UL,
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.phys = 0x40200000UL,
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.size = 0x00100000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* ethernet */
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.virt = 0x40100000UL,
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.phys = 0x40100000UL,
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.size = 0x00100000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* OCVM */
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.virt = 0x80000000UL,
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.phys = 0x80000000UL,
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.size = 0x80000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = corstone1000_mem_map;
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int board_init(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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}
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