Leo Yu-Chi Liang f4512618ca riscv: ae350: Fix XIP config boot failure ... The booting flow is SPL -> OpenSBI -> U-Boot. The boot hart may change after OpenSBI and may not always be hart0, so wrap the related branch instruction with M-MODE. Current DTB setup for XIP is not valid. There is no chance for CONFIG_SYS_FDT_BASE, the DTB address used in XIP mode, to be returned. Fix this. Fixes: 2e8d2f8843 ("riscv: Remove OF_PRIOR_STAGE from RISC-V boards") Signed-off-by: Rick Chen <rick@andestech.com> Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2022-08-11 18:46:07 +08:00
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cpu	riscv: ae350: Fix XIP config boot failure	2022-08-11 18:46:07 +08:00
dts	k210: dts: align plic node with Linux	2022-03-15 17:43:11 +08:00
include/asm	Convert CONFIG_SYS_BOOT_RAMDISK_HIGH to Kconfig	2022-07-07 14:01:09 -04:00
lib	zynqmp: Run board_get_usable_ram_top() only on main U-Boot	2022-07-26 08:23:54 +02:00
config.mk	kconfig / kbuild: Re-sync with Linux 4.19	2020-04-10 11:18:32 -04:00
Kconfig	riscv: alloc space exhausted	2022-04-06 10:58:13 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00