Dinh Nguyen a45526aaa0 arm: socfpga: set the mpuclk divider in the Altera group register ... The mpuclk register in the Altera group of the clock manager divides the mpu_clk that is generated from the C0 output of the main pll. Without this patch, the default value of the register is 1, so the mpuclk will always get divided by 2 if the correct value is not set. For example, on the Arria5 socdk board, the MPU clock is only 525 MHz, and it should be 1.05 GHz. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>		2017-02-08 02:19:11 +01:00
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mach	arm: socfpga: set the mpuclk divider in the Altera group register	2017-02-08 02:19:11 +01:00