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https://github.com/AsahiLinux/u-boot
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f165bc3528
The RCW print is common for all corenet platforms. Not necessary to ducplicate in each board file. Signed-off-by: York Sun <yorksun@freescale.com>
476 lines
10 KiB
C
476 lines
10 KiB
C
/*
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <i2c.h>
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#include <netdev.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include "../common/qixis.h"
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#include "../common/vsc3316_3308.h"
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#include "b4860qds.h"
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#include "b4860qds_qixis.h"
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#include "b4860qds_crossbar_con.h"
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#define CLK_MUX_SEL_MASK 0x4
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#define ETH_PHY_CLK_OUT 0x4
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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char buf[64];
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u8 sw;
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struct cpu_type *cpu = gd->arch.cpu;
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static const char *const freq[] = {"100", "125", "156.25", "161.13",
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"122.88", "122.88", "122.88"};
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int clock;
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printf("Board: %sQDS, ", cpu->name);
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printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, ",
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QIXIS_READ(id), QIXIS_READ(arch));
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sw = QIXIS_READ(brdcfg[0]);
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sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
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if (sw < 0x8)
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printf("vBank: %d\n", sw);
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else if (sw >= 0x8 && sw <= 0xE)
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puts("NAND\n");
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else
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printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
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printf("FPGA: v%d (%s), build %d",
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(int)QIXIS_READ(scver), qixis_read_tag(buf),
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(int)qixis_read_minor());
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/* the timestamp string contains "\n" at the end */
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printf(" on %s", qixis_read_time(buf));
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/*
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* Display the actual SERDES reference clocks as configured by the
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* dip switches on the board. Note that the SWx registers could
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* technically be set to force the reference clocks to match the
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* values that the SERDES expects (or vice versa). For now, however,
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* we just display both values and hope the user notices when they
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* don't match.
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*/
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puts("SERDES Reference Clocks: ");
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sw = QIXIS_READ(brdcfg[2]);
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clock = (sw >> 5) & 7;
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printf("Bank1=%sMHz ", freq[clock]);
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sw = QIXIS_READ(brdcfg[4]);
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clock = (sw >> 6) & 3;
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printf("Bank2=%sMHz\n", freq[clock]);
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return 0;
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}
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int select_i2c_ch_pca(u8 ch)
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{
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int ret;
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/* Selecting proper channel via PCA*/
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ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
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if (ret) {
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printf("PCA: failed to select proper channel.\n");
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return ret;
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}
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return 0;
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}
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int configure_vsc3316_3308(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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unsigned int num_vsc16_con, num_vsc08_con;
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u32 serdes1_prtcl, serdes2_prtcl;
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int ret;
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serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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if (!serdes1_prtcl) {
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printf("SERDES1 is not enabled\n");
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return 0;
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}
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serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
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serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
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if (!serdes2_prtcl) {
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printf("SERDES2 is not enabled\n");
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return 0;
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}
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serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
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debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
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switch (serdes1_prtcl) {
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case 0x2a:
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case 0x2C:
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case 0x2D:
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case 0x2E:
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/*
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* Configuration:
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* SERDES: 1
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* Lanes: A,B: SGMII
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* Lanes: C,D,E,F,G,H: CPRI
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*/
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debug("Configuring crossbar to use onboard SGMII PHYs:"
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"srds_prctl:%x\n", serdes1_prtcl);
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num_vsc16_con = NUM_CON_VSC3316;
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/* Configure VSC3316 crossbar switch */
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ret = select_i2c_ch_pca(I2C_CH_VSC3316);
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if (!ret) {
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ret = vsc3316_config(VSC3316_TX_ADDRESS,
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vsc16_tx_4sfp_sgmii_12_56,
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num_vsc16_con);
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if (ret)
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return ret;
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ret = vsc3316_config(VSC3316_RX_ADDRESS,
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vsc16_rx_4sfp_sgmii_12_56,
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num_vsc16_con);
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if (ret)
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return ret;
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} else {
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return ret;
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}
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break;
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#ifdef CONFIG_PPC_B4420
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case 0x18:
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/*
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* Configuration:
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* SERDES: 1
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* Lanes: A,B,C,D: SGMII
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* Lanes: E,F,G,H: CPRI
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*/
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debug("Configuring crossbar to use onboard SGMII PHYs:"
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"srds_prctl:%x\n", serdes1_prtcl);
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num_vsc16_con = NUM_CON_VSC3316;
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/* Configure VSC3316 crossbar switch */
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ret = select_i2c_ch_pca(I2C_CH_VSC3316);
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if (!ret) {
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ret = vsc3316_config(VSC3316_TX_ADDRESS,
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vsc16_tx_sgmii_lane_cd, num_vsc16_con);
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if (ret)
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return ret;
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ret = vsc3316_config(VSC3316_RX_ADDRESS,
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vsc16_rx_sgmii_lane_cd, num_vsc16_con);
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if (ret)
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return ret;
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} else {
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return ret;
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}
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break;
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#endif
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case 0x3E:
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case 0x0D:
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case 0x0E:
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case 0x12:
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num_vsc16_con = NUM_CON_VSC3316;
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/* Configure VSC3316 crossbar switch */
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ret = select_i2c_ch_pca(I2C_CH_VSC3316);
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if (!ret) {
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ret = vsc3316_config(VSC3316_TX_ADDRESS,
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vsc16_tx_sfp, num_vsc16_con);
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if (ret)
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return ret;
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ret = vsc3316_config(VSC3316_RX_ADDRESS,
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vsc16_rx_sfp, num_vsc16_con);
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if (ret)
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return ret;
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} else {
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return ret;
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}
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break;
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default:
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printf("WARNING:VSC crossbars programming not supported for:%x"
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" SerDes1 Protocol.\n", serdes1_prtcl);
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return -1;
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}
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switch (serdes2_prtcl) {
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case 0x9E:
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case 0x9A:
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case 0x98:
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case 0xb2:
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case 0x49:
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case 0x4E:
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case 0x8D:
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case 0x7A:
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num_vsc08_con = NUM_CON_VSC3308;
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/* Configure VSC3308 crossbar switch */
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ret = select_i2c_ch_pca(I2C_CH_VSC3308);
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if (!ret) {
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ret = vsc3308_config(VSC3308_TX_ADDRESS,
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vsc08_tx_amc, num_vsc08_con);
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if (ret)
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return ret;
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ret = vsc3308_config(VSC3308_RX_ADDRESS,
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vsc08_rx_amc, num_vsc08_con);
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if (ret)
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return ret;
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} else {
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return ret;
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}
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break;
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default:
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printf("WARNING:VSC crossbars programming not supported for: %x"
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" SerDes2 Protocol.\n", serdes2_prtcl);
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return -1;
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}
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return 0;
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash + PROMJET region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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set_liodns();
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#ifdef CONFIG_SYS_DPAA_QBMAN
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setup_portals();
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#endif
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/* Configure VSC3316 and VSC3308 crossbar switches */
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if (configure_vsc3316_3308())
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printf("VSC:failed to configure VSC3316/3308.\n");
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else
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printf("VSC:VSC3316/3308 successfully configured.\n");
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select_i2c_ch_pca(I2C_CH_DEFAULT);
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return 0;
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}
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unsigned long get_board_sys_clk(void)
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{
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u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
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switch ((sysclk_conf & 0x0C) >> 2) {
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case QIXIS_CLK_100:
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return 100000000;
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case QIXIS_CLK_125:
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return 125000000;
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case QIXIS_CLK_133:
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return 133333333;
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}
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return 66666666;
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}
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unsigned long get_board_ddr_clk(void)
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{
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u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
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switch (ddrclk_conf & 0x03) {
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case QIXIS_CLK_100:
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return 100000000;
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case QIXIS_CLK_125:
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return 125000000;
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case QIXIS_CLK_133:
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return 133333333;
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}
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return 66666666;
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}
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static int serdes_refclock(u8 sw, u8 sdclk)
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{
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unsigned int clock;
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int ret = -1;
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u8 brdcfg4;
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if (sdclk == 1) {
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brdcfg4 = QIXIS_READ(brdcfg[4]);
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if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
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return SRDS_PLLCR0_RFCK_SEL_125;
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else
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clock = (sw >> 5) & 7;
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} else
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clock = (sw >> 6) & 3;
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switch (clock) {
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case 0:
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ret = SRDS_PLLCR0_RFCK_SEL_100;
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break;
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case 1:
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ret = SRDS_PLLCR0_RFCK_SEL_125;
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break;
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case 2:
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ret = SRDS_PLLCR0_RFCK_SEL_156_25;
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break;
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case 3:
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ret = SRDS_PLLCR0_RFCK_SEL_161_13;
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break;
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case 4:
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case 5:
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case 6:
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ret = SRDS_PLLCR0_RFCK_SEL_122_88;
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break;
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default:
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ret = -1;
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break;
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}
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return ret;
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}
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static const char *serdes_clock_to_string(u32 clock)
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{
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switch (clock) {
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case SRDS_PLLCR0_RFCK_SEL_100:
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return "100";
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case SRDS_PLLCR0_RFCK_SEL_125:
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return "125";
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case SRDS_PLLCR0_RFCK_SEL_156_25:
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return "156.25";
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case SRDS_PLLCR0_RFCK_SEL_161_13:
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return "161.13";
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default:
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return "122.88";
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}
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}
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#define NUM_SRDS_BANKS 2
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int misc_init_r(void)
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{
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u8 sw;
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serdes_corenet_t *srds_regs =
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(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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u32 actual[NUM_SRDS_BANKS];
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unsigned int i;
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int clock;
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sw = QIXIS_READ(brdcfg[2]);
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clock = serdes_refclock(sw, 1);
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if (clock >= 0)
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actual[0] = clock;
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else
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printf("Warning: SDREFCLK1 switch setting is unsupported\n");
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sw = QIXIS_READ(brdcfg[4]);
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clock = serdes_refclock(sw, 2);
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if (clock >= 0)
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actual[1] = clock;
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else
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printf("Warning: SDREFCLK2 switch setting unsupported\n");
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for (i = 0; i < NUM_SRDS_BANKS; i++) {
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u32 pllcr0 = srds_regs->bank[i].pllcr0;
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u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
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if (expected != actual[i]) {
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printf("Warning: SERDES bank %u expects reference clock"
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" %sMHz, but actual is %sMHz\n", i + 1,
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serdes_clock_to_string(expected),
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serdes_clock_to_string(actual[i]));
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}
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}
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return 0;
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}
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void ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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#ifdef CONFIG_HAS_FSL_DR_USB
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fdt_fixup_dr_usb(blob, bd);
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#endif
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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fdt_fixup_board_enet(blob);
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#endif
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}
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/*
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* Dump board switch settings.
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* The bits that cannot be read/sampled via some FPGA or some
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* registers, they will be displayed as
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* underscore in binary format. mask[] has those bits.
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* Some bits are calculated differently than the actual switches
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* if booting with overriding by FPGA.
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*/
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void qixis_dump_switch(void)
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{
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int i;
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u8 sw[5];
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/*
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* Any bit with 1 means that bit cannot be reverse engineered.
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* It will be displayed as _ in binary format.
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*/
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static const u8 mask[] = {0x07, 0, 0, 0xff, 0};
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char buf[10];
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u8 brdcfg[16], dutcfg[16];
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for (i = 0; i < 16; i++) {
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brdcfg[i] = qixis_read(offsetof(struct qixis, brdcfg[0]) + i);
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dutcfg[i] = qixis_read(offsetof(struct qixis, dutcfg[0]) + i);
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}
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sw[0] = ((brdcfg[0] & 0x0f) << 4) | \
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(brdcfg[9] & 0x08);
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sw[1] = ((dutcfg[1] & 0x01) << 7) | \
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((dutcfg[2] & 0x07) << 4) | \
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((dutcfg[6] & 0x10) >> 1) | \
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((dutcfg[6] & 0x80) >> 5) | \
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((dutcfg[1] & 0x40) >> 5) | \
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(dutcfg[6] & 0x01);
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sw[2] = dutcfg[0];
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sw[3] = 0;
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sw[4] = ((brdcfg[1] & 0x30) << 2) | \
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((brdcfg[1] & 0xc0) >> 2) | \
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(brdcfg[1] & 0x0f);
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puts("DIP switch settings:\n");
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for (i = 0; i < 5; i++) {
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printf("SW%d = 0b%s (0x%02x)\n",
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i + 1, byte_to_binary_mask(sw[i], mask[i], buf), sw[i]);
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}
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}
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