mirror of
https://github.com/AsahiLinux/u-boot
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3c1d218a1d
LS2080A is the primary SoC, and LS2085A is a personality with AIOP and DPAA DDR. The RDB and QDS boards support both personality. By detecting the SVR at runtime, a single image per board can support both SoCs. It gives users flexibility to swtich SoC without the need to reprogram the board. Signed-off-by: York Sun <york.sun@nxp.com> CC: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
225 lines
6.2 KiB
C
225 lines
6.2 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/arch/soc.h>
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#include "ddr.h"
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DECLARE_GLOBAL_DATA_PTR;
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
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#endif
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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int slot;
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if (ctrl_num > 2) {
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printf("Not supported controller number %d\n", ctrl_num);
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return;
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}
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for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
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if (pdimm[slot].n_ranks)
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break;
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}
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if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
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return;
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/*
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* we use identical timing for all slots. If needed, change the code
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* to pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
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*/
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if (popts->registered_dimm_en)
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pbsp = rdimms[ctrl_num];
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else
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pbsp = udimms[ctrl_num];
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/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm[slot].n_ranks &&
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(pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found for data rate %lu MT/s\n"
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"Trying to use the highest speed (%u) parameters\n",
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ddr_freq, pbsp_highest->datarate_mhz_high);
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popts->clk_adjust = pbsp_highest->clk_adjust;
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popts->wrlvl_start = pbsp_highest->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
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"\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
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pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
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pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
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pbsp->wrlvl_ctl_3);
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#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
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if (ctrl_num == CONFIG_DP_DDR_CTRL) {
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/* force DDR bus width to 32 bits */
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popts->data_bus_width = 1;
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popts->otf_burst_chop_en = 0;
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popts->burst_length = DDR_BL8;
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popts->bstopre = 0; /* enable auto precharge */
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/*
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* Layout optimization results byte mapping
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* Byte 0 -> Byte ECC
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* Byte 1 -> Byte 3
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* Byte 2 -> Byte 2
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* Byte 3 -> Byte 1
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* Byte ECC -> Byte 0
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*/
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dq_mapping_0 = pdimm[slot].dq_mapping[0];
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dq_mapping_2 = pdimm[slot].dq_mapping[2];
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dq_mapping_3 = pdimm[slot].dq_mapping[3];
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pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
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pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
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pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
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pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
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pdimm[slot].dq_mapping[6] = dq_mapping_2;
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pdimm[slot].dq_mapping[7] = dq_mapping_3;
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pdimm[slot].dq_mapping[8] = dq_mapping_0;
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pdimm[slot].dq_mapping[9] = 0;
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pdimm[slot].dq_mapping[10] = 0;
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pdimm[slot].dq_mapping[11] = 0;
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pdimm[slot].dq_mapping[12] = 0;
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pdimm[slot].dq_mapping[13] = 0;
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pdimm[slot].dq_mapping[14] = 0;
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pdimm[slot].dq_mapping[15] = 0;
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pdimm[slot].dq_mapping[16] = 0;
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pdimm[slot].dq_mapping[17] = 0;
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}
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#endif
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/* To work at higher than 1333MT/s */
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popts->half_strength_driver_enable = 0;
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/*
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* Write leveling override
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*/
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0x0; /* 32 clocks */
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/*
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* Rtt and Rtt_WR override
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*/
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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if (ddr_freq < 2350) {
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if (pdimm[0].n_ranks == 2 && pdimm[1].n_ranks == 2) {
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/* four chip-selects */
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
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DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm);
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popts->twot_en = 1; /* enable 2T timing */
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} else {
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
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DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
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DDR_CDR2_VREF_RANGE_2;
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}
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} else {
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
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DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
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DDR_CDR2_VREF_RANGE_2;
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}
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size;
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#if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
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return fsl_ddr_sdram_size();
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#else
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puts("Initializing DDR....using SPD\n");
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dram_size = fsl_ddr_sdram();
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#endif
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return dram_size;
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}
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void dram_init_banksize(void)
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{
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#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
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phys_size_t dp_ddr_size;
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#endif
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/*
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* gd->secure_ram tracks the location of secure memory.
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* It was set as if the memory starts from 0.
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* The address needs to add the offset of its bank.
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*/
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
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gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
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gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
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gd->bd->bi_dram[1].size = gd->ram_size -
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CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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gd->secure_ram = gd->bd->bi_dram[1].start +
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gd->secure_ram -
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CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
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gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
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#endif
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} else {
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gd->bd->bi_dram[0].size = gd->ram_size;
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#ifdef CONFIG_SYS_MEM_RESERVE_SECURE
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gd->secure_ram = gd->bd->bi_dram[0].start + gd->secure_ram;
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gd->secure_ram |= MEM_RESERVE_SECURE_MAINTAINED;
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#endif
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}
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#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
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if (soc_has_dp_ddr()) {
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/* initialize DP-DDR here */
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puts("DP-DDR: ");
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/*
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* DDR controller use 0 as the base address for binding.
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* It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
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*/
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dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
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CONFIG_DP_DDR_CTRL,
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CONFIG_DP_DDR_NUM_CTRLS,
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CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
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NULL, NULL, NULL);
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if (dp_ddr_size) {
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gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
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gd->bd->bi_dram[2].size = dp_ddr_size;
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} else {
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puts("Not detected");
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}
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}
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#endif
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}
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