mirror of
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f0d49d4f0d
Add missing include for dm/device_compat.h. Without this include the SFC driver fails to compile because dev_err and dev_dbg are not defined. Signed-off-by: Chris Morgan <macromorgan@hotmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
646 lines
15 KiB
C
646 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip Serial Flash Controller Driver
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*
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* Copyright (c) 2017-2021, Rockchip Inc.
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* Author: Shawn Lin <shawn.lin@rock-chips.com>
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* Chris Morgan <macromorgan@hotmail.com>
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* Jon Lin <Jon.lin@rock-chips.com>
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*/
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#include <asm/io.h>
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#include <bouncebuf.h>
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#include <clk.h>
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#include <dm.h>
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#include <dm/device_compat.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/iopoll.h>
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#include <spi.h>
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#include <spi-mem.h>
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/* System control */
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#define SFC_CTRL 0x0
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#define SFC_CTRL_PHASE_SEL_NEGETIVE BIT(1)
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#define SFC_CTRL_CMD_BITS_SHIFT 8
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#define SFC_CTRL_ADDR_BITS_SHIFT 10
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#define SFC_CTRL_DATA_BITS_SHIFT 12
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/* Interrupt mask */
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#define SFC_IMR 0x4
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#define SFC_IMR_RX_FULL BIT(0)
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#define SFC_IMR_RX_UFLOW BIT(1)
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#define SFC_IMR_TX_OFLOW BIT(2)
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#define SFC_IMR_TX_EMPTY BIT(3)
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#define SFC_IMR_TRAN_FINISH BIT(4)
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#define SFC_IMR_BUS_ERR BIT(5)
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#define SFC_IMR_NSPI_ERR BIT(6)
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#define SFC_IMR_DMA BIT(7)
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/* Interrupt clear */
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#define SFC_ICLR 0x8
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#define SFC_ICLR_RX_FULL BIT(0)
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#define SFC_ICLR_RX_UFLOW BIT(1)
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#define SFC_ICLR_TX_OFLOW BIT(2)
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#define SFC_ICLR_TX_EMPTY BIT(3)
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#define SFC_ICLR_TRAN_FINISH BIT(4)
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#define SFC_ICLR_BUS_ERR BIT(5)
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#define SFC_ICLR_NSPI_ERR BIT(6)
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#define SFC_ICLR_DMA BIT(7)
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/* FIFO threshold level */
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#define SFC_FTLR 0xc
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#define SFC_FTLR_TX_SHIFT 0
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#define SFC_FTLR_TX_MASK 0x1f
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#define SFC_FTLR_RX_SHIFT 8
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#define SFC_FTLR_RX_MASK 0x1f
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/* Reset FSM and FIFO */
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#define SFC_RCVR 0x10
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#define SFC_RCVR_RESET BIT(0)
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/* Enhanced mode */
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#define SFC_AX 0x14
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/* Address Bit number */
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#define SFC_ABIT 0x18
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/* Interrupt status */
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#define SFC_ISR 0x1c
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#define SFC_ISR_RX_FULL_SHIFT BIT(0)
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#define SFC_ISR_RX_UFLOW_SHIFT BIT(1)
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#define SFC_ISR_TX_OFLOW_SHIFT BIT(2)
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#define SFC_ISR_TX_EMPTY_SHIFT BIT(3)
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#define SFC_ISR_TX_FINISH_SHIFT BIT(4)
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#define SFC_ISR_BUS_ERR_SHIFT BIT(5)
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#define SFC_ISR_NSPI_ERR_SHIFT BIT(6)
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#define SFC_ISR_DMA_SHIFT BIT(7)
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/* FIFO status */
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#define SFC_FSR 0x20
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#define SFC_FSR_TX_IS_FULL BIT(0)
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#define SFC_FSR_TX_IS_EMPTY BIT(1)
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#define SFC_FSR_RX_IS_EMPTY BIT(2)
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#define SFC_FSR_RX_IS_FULL BIT(3)
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#define SFC_FSR_TXLV_MASK GENMASK(12, 8)
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#define SFC_FSR_TXLV_SHIFT 8
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#define SFC_FSR_RXLV_MASK GENMASK(20, 16)
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#define SFC_FSR_RXLV_SHIFT 16
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/* FSM status */
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#define SFC_SR 0x24
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#define SFC_SR_IS_IDLE 0x0
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#define SFC_SR_IS_BUSY 0x1
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/* Raw interrupt status */
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#define SFC_RISR 0x28
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#define SFC_RISR_RX_FULL BIT(0)
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#define SFC_RISR_RX_UNDERFLOW BIT(1)
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#define SFC_RISR_TX_OVERFLOW BIT(2)
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#define SFC_RISR_TX_EMPTY BIT(3)
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#define SFC_RISR_TRAN_FINISH BIT(4)
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#define SFC_RISR_BUS_ERR BIT(5)
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#define SFC_RISR_NSPI_ERR BIT(6)
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#define SFC_RISR_DMA BIT(7)
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/* Version */
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#define SFC_VER 0x2C
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#define SFC_VER_3 0x3
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#define SFC_VER_4 0x4
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#define SFC_VER_5 0x5
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/* Delay line controller resiter */
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#define SFC_DLL_CTRL0 0x3C
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#define SFC_DLL_CTRL0_SCLK_SMP_DLL BIT(15)
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#define SFC_DLL_CTRL0_DLL_MAX_VER4 0xFFU
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#define SFC_DLL_CTRL0_DLL_MAX_VER5 0x1FFU
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/* Master trigger */
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#define SFC_DMA_TRIGGER 0x80
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#define SFC_DMA_TRIGGER_START 1
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/* Src or Dst addr for master */
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#define SFC_DMA_ADDR 0x84
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/* Length control register extension 32GB */
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#define SFC_LEN_CTRL 0x88
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#define SFC_LEN_CTRL_TRB_SEL 1
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#define SFC_LEN_EXT 0x8C
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/* Command */
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#define SFC_CMD 0x100
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#define SFC_CMD_IDX_SHIFT 0
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#define SFC_CMD_DUMMY_SHIFT 8
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#define SFC_CMD_DIR_SHIFT 12
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#define SFC_CMD_DIR_RD 0
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#define SFC_CMD_DIR_WR 1
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#define SFC_CMD_ADDR_SHIFT 14
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#define SFC_CMD_ADDR_0BITS 0
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#define SFC_CMD_ADDR_24BITS 1
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#define SFC_CMD_ADDR_32BITS 2
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#define SFC_CMD_ADDR_XBITS 3
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#define SFC_CMD_TRAN_BYTES_SHIFT 16
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#define SFC_CMD_CS_SHIFT 30
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/* Address */
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#define SFC_ADDR 0x104
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/* Data */
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#define SFC_DATA 0x108
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/* The controller and documentation reports that it supports up to 4 CS
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* devices (0-3), however I have only been able to test a single CS (CS 0)
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* due to the configuration of my device.
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*/
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#define SFC_MAX_CHIPSELECT_NUM 4
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/* The SFC can transfer max 16KB - 1 at one time
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* we set it to 15.5KB here for alignment.
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*/
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#define SFC_MAX_IOSIZE_VER3 (512 * 31)
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#define SFC_MAX_IOSIZE_VER4 (0xFFFFFFFFU)
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/* DMA is only enabled for large data transmission */
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#define SFC_DMA_TRANS_THRETHOLD (0x40)
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/* Maximum clock values from datasheet suggest keeping clock value under
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* 150MHz. No minimum or average value is suggested.
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*/
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#define SFC_MAX_SPEED (150 * 1000 * 1000)
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struct rockchip_sfc {
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struct udevice *dev;
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void __iomem *regbase;
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struct clk hclk;
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struct clk clk;
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u32 max_freq;
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u32 speed;
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bool use_dma;
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u32 max_iosize;
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u16 version;
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};
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static int rockchip_sfc_reset(struct rockchip_sfc *sfc)
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{
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int err;
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u32 status;
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writel(SFC_RCVR_RESET, sfc->regbase + SFC_RCVR);
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err = readl_poll_timeout(sfc->regbase + SFC_RCVR, status,
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!(status & SFC_RCVR_RESET),
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1000000);
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if (err)
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printf("SFC reset never finished\n");
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/* Still need to clear the masked interrupt from RISR */
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writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
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return err;
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}
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static u16 rockchip_sfc_get_version(struct rockchip_sfc *sfc)
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{
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return (u16)(readl(sfc->regbase + SFC_VER) & 0xffff);
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}
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static u32 rockchip_sfc_get_max_iosize(struct rockchip_sfc *sfc)
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{
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if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
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return SFC_MAX_IOSIZE_VER4;
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return SFC_MAX_IOSIZE_VER3;
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}
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static int rockchip_sfc_init(struct rockchip_sfc *sfc)
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{
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writel(0, sfc->regbase + SFC_CTRL);
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if (rockchip_sfc_get_version(sfc) >= SFC_VER_4)
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writel(SFC_LEN_CTRL_TRB_SEL, sfc->regbase + SFC_LEN_CTRL);
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return 0;
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}
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static int rockchip_sfc_ofdata_to_platdata(struct udevice *bus)
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{
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struct rockchip_sfc *sfc = dev_get_plat(bus);
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sfc->regbase = dev_read_addr_ptr(bus);
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if (ofnode_read_bool(dev_ofnode(bus), "sfc-no-dma"))
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sfc->use_dma = false;
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else
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sfc->use_dma = true;
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#if CONFIG_IS_ENABLED(CLK)
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int ret;
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ret = clk_get_by_index(bus, 0, &sfc->clk);
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if (ret < 0) {
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printf("Could not get clock for %s: %d\n", bus->name, ret);
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return ret;
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}
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ret = clk_get_by_index(bus, 1, &sfc->hclk);
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if (ret < 0) {
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printf("Could not get ahb clock for %s: %d\n", bus->name, ret);
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return ret;
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}
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#endif
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return 0;
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}
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static int rockchip_sfc_probe(struct udevice *bus)
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{
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struct rockchip_sfc *sfc = dev_get_plat(bus);
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int ret;
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_enable(&sfc->hclk);
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if (ret)
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dev_dbg(sfc->dev, "sfc Enable ahb clock fail %s: %d\n", bus->name, ret);
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ret = clk_enable(&sfc->clk);
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if (ret)
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dev_dbg(sfc->dev, "sfc Enable clock fail for %s: %d\n", bus->name, ret);
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#endif
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ret = rockchip_sfc_init(sfc);
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if (ret)
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goto err_init;
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sfc->max_iosize = rockchip_sfc_get_max_iosize(sfc);
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sfc->version = rockchip_sfc_get_version(sfc);
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sfc->max_freq = SFC_MAX_SPEED;
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sfc->dev = bus;
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return 0;
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err_init:
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#if CONFIG_IS_ENABLED(CLK)
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clk_disable(&sfc->clk);
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clk_disable(&sfc->hclk);
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#endif
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return ret;
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}
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static int rockchip_sfc_wait_txfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
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{
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int ret = 0;
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u32 status;
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ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
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status & SFC_FSR_TXLV_MASK,
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timeout_us);
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if (ret) {
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dev_dbg(sfc->dev, "sfc wait tx fifo timeout\n");
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return -ETIMEDOUT;
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}
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return (status & SFC_FSR_TXLV_MASK) >> SFC_FSR_TXLV_SHIFT;
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}
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static int rockchip_sfc_wait_rxfifo_ready(struct rockchip_sfc *sfc, u32 timeout_us)
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{
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int ret = 0;
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u32 status;
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ret = readl_poll_timeout(sfc->regbase + SFC_FSR, status,
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status & SFC_FSR_RXLV_MASK,
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timeout_us);
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if (ret) {
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dev_dbg(sfc->dev, "sfc wait rx fifo timeout\n");
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return -ETIMEDOUT;
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}
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return (status & SFC_FSR_RXLV_MASK) >> SFC_FSR_RXLV_SHIFT;
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}
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static void rockchip_sfc_adjust_op_work(struct spi_mem_op *op)
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{
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if (unlikely(op->dummy.nbytes && !op->addr.nbytes)) {
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/*
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* SFC not support output DUMMY cycles right after CMD cycles, so
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* treat it as ADDR cycles.
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*/
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op->addr.nbytes = op->dummy.nbytes;
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op->addr.buswidth = op->dummy.buswidth;
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op->addr.val = 0xFFFFFFFFF;
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op->dummy.nbytes = 0;
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}
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}
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static int rockchip_sfc_wait_for_dma_finished(struct rockchip_sfc *sfc, int timeout)
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{
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unsigned long tbase;
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/* Wait for the DMA interrupt status */
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tbase = get_timer(0);
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while (!(readl(sfc->regbase + SFC_RISR) & SFC_RISR_DMA)) {
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if (get_timer(tbase) > timeout) {
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printf("dma timeout\n");
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rockchip_sfc_reset(sfc);
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return -ETIMEDOUT;
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}
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udelay(1);
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}
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writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
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return 0;
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}
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static int rockchip_sfc_xfer_setup(struct rockchip_sfc *sfc,
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struct spi_slave *mem,
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const struct spi_mem_op *op,
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u32 len)
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{
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struct dm_spi_slave_plat *plat = dev_get_parent_plat(mem->dev);
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u32 ctrl = 0, cmd = 0;
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/* set CMD */
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cmd = op->cmd.opcode;
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ctrl |= ((op->cmd.buswidth >> 1) << SFC_CTRL_CMD_BITS_SHIFT);
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/* set ADDR */
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if (op->addr.nbytes) {
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if (op->addr.nbytes == 4) {
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cmd |= SFC_CMD_ADDR_32BITS << SFC_CMD_ADDR_SHIFT;
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} else if (op->addr.nbytes == 3) {
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cmd |= SFC_CMD_ADDR_24BITS << SFC_CMD_ADDR_SHIFT;
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} else {
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cmd |= SFC_CMD_ADDR_XBITS << SFC_CMD_ADDR_SHIFT;
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writel(op->addr.nbytes * 8 - 1, sfc->regbase + SFC_ABIT);
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}
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ctrl |= ((op->addr.buswidth >> 1) << SFC_CTRL_ADDR_BITS_SHIFT);
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}
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/* set DUMMY */
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if (op->dummy.nbytes) {
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if (op->dummy.buswidth == 4)
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cmd |= op->dummy.nbytes * 2 << SFC_CMD_DUMMY_SHIFT;
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else if (op->dummy.buswidth == 2)
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cmd |= op->dummy.nbytes * 4 << SFC_CMD_DUMMY_SHIFT;
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else
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cmd |= op->dummy.nbytes * 8 << SFC_CMD_DUMMY_SHIFT;
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}
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/* set DATA */
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if (sfc->version >= SFC_VER_4) /* Clear it if no data to transfer */
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writel(len, sfc->regbase + SFC_LEN_EXT);
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else
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cmd |= len << SFC_CMD_TRAN_BYTES_SHIFT;
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if (len) {
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if (op->data.dir == SPI_MEM_DATA_OUT)
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cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
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ctrl |= ((op->data.buswidth >> 1) << SFC_CTRL_DATA_BITS_SHIFT);
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}
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if (!len && op->addr.nbytes)
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cmd |= SFC_CMD_DIR_WR << SFC_CMD_DIR_SHIFT;
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/* set the Controller */
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ctrl |= SFC_CTRL_PHASE_SEL_NEGETIVE;
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cmd |= plat->cs << SFC_CMD_CS_SHIFT;
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dev_dbg(sfc->dev, "sfc addr.nbytes=%x(x%d) dummy.nbytes=%x(x%d)\n",
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op->addr.nbytes, op->addr.buswidth,
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op->dummy.nbytes, op->dummy.buswidth);
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dev_dbg(sfc->dev, "sfc ctrl=%x cmd=%x addr=%llx len=%x\n",
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ctrl, cmd, op->addr.val, len);
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writel(ctrl, sfc->regbase + SFC_CTRL);
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writel(cmd, sfc->regbase + SFC_CMD);
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if (op->addr.nbytes)
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writel(op->addr.val, sfc->regbase + SFC_ADDR);
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return 0;
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}
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static int rockchip_sfc_write_fifo(struct rockchip_sfc *sfc, const u8 *buf, int len)
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{
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u8 bytes = len & 0x3;
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u32 dwords;
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int tx_level;
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u32 write_words;
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u32 tmp = 0;
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dwords = len >> 2;
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while (dwords) {
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tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
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if (tx_level < 0)
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return tx_level;
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write_words = min_t(u32, tx_level, dwords);
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writesl(sfc->regbase + SFC_DATA, buf, write_words);
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buf += write_words << 2;
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dwords -= write_words;
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}
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/* write the rest non word aligned bytes */
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if (bytes) {
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tx_level = rockchip_sfc_wait_txfifo_ready(sfc, 1000);
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if (tx_level < 0)
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return tx_level;
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memcpy(&tmp, buf, bytes);
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writel(tmp, sfc->regbase + SFC_DATA);
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}
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return len;
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}
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static int rockchip_sfc_read_fifo(struct rockchip_sfc *sfc, u8 *buf, int len)
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{
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u8 bytes = len & 0x3;
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u32 dwords;
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u8 read_words;
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int rx_level;
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int tmp;
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/* word aligned access only */
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dwords = len >> 2;
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while (dwords) {
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rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
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if (rx_level < 0)
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return rx_level;
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read_words = min_t(u32, rx_level, dwords);
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readsl(sfc->regbase + SFC_DATA, buf, read_words);
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buf += read_words << 2;
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dwords -= read_words;
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}
|
|
|
|
/* read the rest non word aligned bytes */
|
|
if (bytes) {
|
|
rx_level = rockchip_sfc_wait_rxfifo_ready(sfc, 1000);
|
|
if (rx_level < 0)
|
|
return rx_level;
|
|
tmp = readl(sfc->regbase + SFC_DATA);
|
|
memcpy(buf, &tmp, bytes);
|
|
}
|
|
|
|
return len;
|
|
}
|
|
|
|
static int rockchip_sfc_fifo_transfer_dma(struct rockchip_sfc *sfc, dma_addr_t dma_buf, size_t len)
|
|
{
|
|
writel(0xFFFFFFFF, sfc->regbase + SFC_ICLR);
|
|
writel((u32)dma_buf, sfc->regbase + SFC_DMA_ADDR);
|
|
writel(SFC_DMA_TRIGGER_START, sfc->regbase + SFC_DMA_TRIGGER);
|
|
|
|
return len;
|
|
}
|
|
|
|
static int rockchip_sfc_xfer_data_poll(struct rockchip_sfc *sfc,
|
|
const struct spi_mem_op *op, u32 len)
|
|
{
|
|
dev_dbg(sfc->dev, "sfc xfer_poll len=%x\n", len);
|
|
|
|
if (op->data.dir == SPI_MEM_DATA_OUT)
|
|
return rockchip_sfc_write_fifo(sfc, op->data.buf.out, len);
|
|
else
|
|
return rockchip_sfc_read_fifo(sfc, op->data.buf.in, len);
|
|
}
|
|
|
|
static int rockchip_sfc_xfer_data_dma(struct rockchip_sfc *sfc,
|
|
const struct spi_mem_op *op, u32 len)
|
|
{
|
|
struct bounce_buffer bb;
|
|
unsigned int bb_flags;
|
|
void *dma_buf;
|
|
int ret;
|
|
|
|
dev_dbg(sfc->dev, "sfc xfer_dma len=%x\n", len);
|
|
|
|
if (op->data.dir == SPI_MEM_DATA_OUT) {
|
|
dma_buf = (void *)op->data.buf.out;
|
|
bb_flags = GEN_BB_READ;
|
|
} else {
|
|
dma_buf = (void *)op->data.buf.in;
|
|
bb_flags = GEN_BB_WRITE;
|
|
}
|
|
|
|
ret = bounce_buffer_start(&bb, dma_buf, len, bb_flags);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = rockchip_sfc_fifo_transfer_dma(sfc, (dma_addr_t)bb.bounce_buffer, len);
|
|
rockchip_sfc_wait_for_dma_finished(sfc, len * 10);
|
|
bounce_buffer_stop(&bb);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rockchip_sfc_xfer_done(struct rockchip_sfc *sfc, u32 timeout_us)
|
|
{
|
|
int ret = 0;
|
|
u32 status;
|
|
|
|
ret = readl_poll_timeout(sfc->regbase + SFC_SR, status,
|
|
!(status & SFC_SR_IS_BUSY),
|
|
timeout_us);
|
|
if (ret) {
|
|
dev_err(sfc->dev, "wait sfc idle timeout\n");
|
|
rockchip_sfc_reset(sfc);
|
|
|
|
ret = -EIO;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rockchip_sfc_exec_op(struct spi_slave *mem,
|
|
const struct spi_mem_op *op)
|
|
{
|
|
struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
|
|
u32 len = min_t(u32, op->data.nbytes, sfc->max_iosize);
|
|
int ret;
|
|
|
|
rockchip_sfc_adjust_op_work((struct spi_mem_op *)op);
|
|
rockchip_sfc_xfer_setup(sfc, mem, op, len);
|
|
if (len) {
|
|
if (likely(sfc->use_dma) && len >= SFC_DMA_TRANS_THRETHOLD)
|
|
ret = rockchip_sfc_xfer_data_dma(sfc, op, len);
|
|
else
|
|
ret = rockchip_sfc_xfer_data_poll(sfc, op, len);
|
|
|
|
if (ret != len) {
|
|
dev_err(sfc->dev, "xfer data failed ret %d dir %d\n", ret, op->data.dir);
|
|
|
|
return -EIO;
|
|
}
|
|
}
|
|
|
|
return rockchip_sfc_xfer_done(sfc, 100000);
|
|
}
|
|
|
|
static int rockchip_sfc_adjust_op_size(struct spi_slave *mem, struct spi_mem_op *op)
|
|
{
|
|
struct rockchip_sfc *sfc = dev_get_plat(mem->dev->parent);
|
|
|
|
op->data.nbytes = min(op->data.nbytes, sfc->max_iosize);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_sfc_set_speed(struct udevice *bus, uint speed)
|
|
{
|
|
struct rockchip_sfc *sfc = dev_get_plat(bus);
|
|
|
|
if (speed > sfc->max_freq)
|
|
speed = sfc->max_freq;
|
|
|
|
if (speed == sfc->speed)
|
|
return 0;
|
|
|
|
#if CONFIG_IS_ENABLED(CLK)
|
|
int ret = clk_set_rate(&sfc->clk, speed);
|
|
|
|
if (ret < 0) {
|
|
dev_err(sfc->dev, "set_freq=%dHz fail, check if it's the cru support level\n",
|
|
speed);
|
|
return ret;
|
|
}
|
|
sfc->speed = speed;
|
|
#else
|
|
dev_dbg(sfc->dev, "sfc failed, CLK not support\n");
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_sfc_set_mode(struct udevice *bus, uint mode)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct spi_controller_mem_ops rockchip_sfc_mem_ops = {
|
|
.adjust_op_size = rockchip_sfc_adjust_op_size,
|
|
.exec_op = rockchip_sfc_exec_op,
|
|
};
|
|
|
|
static const struct dm_spi_ops rockchip_sfc_ops = {
|
|
.mem_ops = &rockchip_sfc_mem_ops,
|
|
.set_speed = rockchip_sfc_set_speed,
|
|
.set_mode = rockchip_sfc_set_mode,
|
|
};
|
|
|
|
static const struct udevice_id rockchip_sfc_ids[] = {
|
|
{ .compatible = "rockchip,sfc"},
|
|
{},
|
|
};
|
|
|
|
U_BOOT_DRIVER(rockchip_sfc_driver) = {
|
|
.name = "rockchip_sfc",
|
|
.id = UCLASS_SPI,
|
|
.of_match = rockchip_sfc_ids,
|
|
.ops = &rockchip_sfc_ops,
|
|
.of_to_plat = rockchip_sfc_ofdata_to_platdata,
|
|
.plat_auto = sizeof(struct rockchip_sfc),
|
|
.probe = rockchip_sfc_probe,
|
|
};
|