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As of today, the latest version FSP (gold4) for BayTrail misses the PAD configuration of the SD controller's Card Detect signal. The default PAD value for the CD pin sets the pin to work in GPIO mode, which causes card detect status cannot be reflected by the Present State register in the SD controller (bit 16 & bit 18 are always zero). Add a configuration for this pin in the pinctrl node. Note I've checked the PAD configuration for all the pins in all the 3 controllers (eMMC/SDIO/SD). Only this SDMMC3_CD_B pin does not get initialized to correct mode by FSP. With fsp,emmc-boot-mode set to 2 (eMMC 4.1), eMMC pins are initialized to func 1, but if we set fsp,emmc-boot-mode to 1 (auto), those pins are initialized to func 3 which is correct according to datasheet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> |
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| .. | ||
| include | ||
| microcode | ||
| .gitignore | ||
| bayleybay.dts | ||
| broadwell_som-6896.dts | ||
| chromebook_link.dts | ||
| chromebook_samus.dts | ||
| chromebox_panther.dts | ||
| conga-qeval20-qa3-e3845.dts | ||
| cougarcanyon2.dts | ||
| crownbay.dts | ||
| efi.dts | ||
| galileo.dts | ||
| keyboard.dtsi | ||
| Makefile | ||
| minnowmax.dts | ||
| qemu-x86_i440fx.dts | ||
| qemu-x86_q35.dts | ||
| rtc.dtsi | ||
| serial.dtsi | ||
| skeleton.dtsi | ||
| tsc_timer.dtsi | ||