mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 15:37:23 +00:00
c369139234
Some Tegra device tree files do not include information about the serial ports. Add this and also add information about the input clock speed. The console alias needs to be set up to indicate which port is used for the console. Also add a binding file since this is missing. Series-changes; 5 - Add full serial port nodes from Linux tree (commit fc9d4dbe) - Use /chosen/stdout-path instead of /aliases/console to specify the console Signed-off-by: Simon Glass <sjg@chromium.org>
391 lines
8.5 KiB
Text
391 lines
8.5 KiB
Text
#include <dt-bindings/clock/tegra20-car.h>
|
|
#include <dt-bindings/gpio/tegra-gpio.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
#include "skeleton.dtsi"
|
|
|
|
/ {
|
|
compatible = "nvidia,tegra20";
|
|
interrupt-parent = <&intc>;
|
|
|
|
host1x {
|
|
compatible = "nvidia,tegra20-host1x", "simple-bus";
|
|
reg = <0x50000000 0x00024000>;
|
|
interrupts = <0 65 0x04 /* mpcore syncpt */
|
|
0 67 0x04>; /* mpcore general */
|
|
status = "disabled";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0x54000000 0x54000000 0x04000000>;
|
|
|
|
/* video-encoding/decoding */
|
|
mpe {
|
|
reg = <0x54040000 0x00040000>;
|
|
interrupts = <0 68 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* video input */
|
|
vi {
|
|
reg = <0x54080000 0x00040000>;
|
|
interrupts = <0 69 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* EPP */
|
|
epp {
|
|
reg = <0x540c0000 0x00040000>;
|
|
interrupts = <0 70 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* ISP */
|
|
isp {
|
|
reg = <0x54100000 0x00040000>;
|
|
interrupts = <0 71 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* 2D engine */
|
|
gr2d {
|
|
reg = <0x54140000 0x00040000>;
|
|
interrupts = <0 72 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* 3D engine */
|
|
gr3d {
|
|
reg = <0x54180000 0x00040000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* display controllers */
|
|
dc@54200000 {
|
|
compatible = "nvidia,tegra20-dc";
|
|
reg = <0x54200000 0x00040000>;
|
|
interrupts = <0 73 0x04>;
|
|
status = "disabled";
|
|
|
|
rgb {
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
dc@54240000 {
|
|
compatible = "nvidia,tegra20-dc";
|
|
reg = <0x54240000 0x00040000>;
|
|
interrupts = <0 74 0x04>;
|
|
status = "disabled";
|
|
|
|
rgb {
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
/* outputs */
|
|
hdmi {
|
|
compatible = "nvidia,tegra20-hdmi";
|
|
reg = <0x54280000 0x00040000>;
|
|
interrupts = <0 75 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tvo {
|
|
compatible = "nvidia,tegra20-tvo";
|
|
reg = <0x542c0000 0x00040000>;
|
|
interrupts = <0 76 0x04>;
|
|
status = "disabled";
|
|
};
|
|
|
|
dsi {
|
|
compatible = "nvidia,tegra20-dsi";
|
|
reg = <0x54300000 0x00040000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
intc: interrupt-controller@50041000 {
|
|
compatible = "nvidia,tegra20-gic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
reg = < 0x50041000 0x1000 >,
|
|
< 0x50040100 0x0100 >;
|
|
};
|
|
|
|
tegra_car: clock@60006000 {
|
|
compatible = "nvidia,tegra20-car";
|
|
reg = <0x60006000 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
apbdma: dma {
|
|
compatible = "nvidia,tegra20-apbdma";
|
|
reg = <0x6000a000 0x1200>;
|
|
interrupts = <0 104 0x04
|
|
0 105 0x04
|
|
0 106 0x04
|
|
0 107 0x04
|
|
0 108 0x04
|
|
0 109 0x04
|
|
0 110 0x04
|
|
0 111 0x04
|
|
0 112 0x04
|
|
0 113 0x04
|
|
0 114 0x04
|
|
0 115 0x04
|
|
0 116 0x04
|
|
0 117 0x04
|
|
0 118 0x04
|
|
0 119 0x04>;
|
|
};
|
|
|
|
gpio: gpio@6000d000 {
|
|
compatible = "nvidia,tegra20-gpio";
|
|
reg = <0x6000d000 0x1000>;
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
pinmux: pinmux@70000000 {
|
|
compatible = "nvidia,tegra20-pinmux";
|
|
reg = < 0x70000014 0x10 /* Tri-state registers */
|
|
0x70000080 0x20 /* Mux registers */
|
|
0x700000a0 0x14 /* Pull-up/down registers */
|
|
0x70000868 0xa8 >; /* Pad control registers */
|
|
};
|
|
|
|
das@70000c00 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "nvidia,tegra20-das";
|
|
reg = <0x70000c00 0x80>;
|
|
};
|
|
|
|
i2s@70002800 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "nvidia,tegra20-i2s";
|
|
reg = <0x70002800 0x200>;
|
|
interrupts = < 45 >;
|
|
dma-channel = < 2 >;
|
|
};
|
|
|
|
i2s@70002a00 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "nvidia,tegra20-i2s";
|
|
reg = <0x70002a00 0x200>;
|
|
interrupts = < 35 >;
|
|
dma-channel = < 1 >;
|
|
};
|
|
|
|
uarta: serial@70006000 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006000 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTA>;
|
|
resets = <&tegra_car 6>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 8>, <&apbdma 8>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uartb: serial@70006040 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006040 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTB>;
|
|
resets = <&tegra_car 7>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 9>, <&apbdma 9>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uartc: serial@70006200 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006200 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTC>;
|
|
resets = <&tegra_car 55>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 10>, <&apbdma 10>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uartd: serial@70006300 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006300 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTD>;
|
|
resets = <&tegra_car 65>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 19>, <&apbdma 19>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
uarte: serial@70006400 {
|
|
compatible = "nvidia,tegra20-uart";
|
|
reg = <0x70006400 0x100>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_UARTE>;
|
|
resets = <&tegra_car 66>;
|
|
reset-names = "serial";
|
|
dmas = <&apbdma 20>, <&apbdma 20>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
|
|
nand: nand-controller@70008000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "nvidia,tegra20-nand";
|
|
reg = <0x70008000 0x100>;
|
|
};
|
|
|
|
pwm: pwm@7000a000 {
|
|
compatible = "nvidia,tegra20-pwm";
|
|
reg = <0x7000a000 0x100>;
|
|
#pwm-cells = <2>;
|
|
};
|
|
|
|
i2c@7000c000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "nvidia,tegra20-i2c";
|
|
reg = <0x7000C000 0x100>;
|
|
interrupts = < 70 >;
|
|
/* PERIPH_ID_I2C1, PLL_P_OUT3 */
|
|
clocks = <&tegra_car 12>, <&tegra_car 124>;
|
|
};
|
|
|
|
spi@7000c380 {
|
|
compatible = "nvidia,tegra20-sflash";
|
|
reg = <0x7000c380 0x80>;
|
|
interrupts = <0 39 0x04>;
|
|
nvidia,dma-request-selector = <&apbdma 11>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
/* PERIPH_ID_SPI1, PLLP_OUT0 */
|
|
clocks = <&tegra_car 43>;
|
|
};
|
|
|
|
i2c@7000c400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "nvidia,tegra20-i2c";
|
|
reg = <0x7000C400 0x100>;
|
|
interrupts = < 116 >;
|
|
/* PERIPH_ID_I2C2, PLL_P_OUT3 */
|
|
clocks = <&tegra_car 54>, <&tegra_car 124>;
|
|
};
|
|
|
|
i2c@7000c500 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "nvidia,tegra20-i2c";
|
|
reg = <0x7000C500 0x100>;
|
|
interrupts = < 124 >;
|
|
/* PERIPH_ID_I2C3, PLL_P_OUT3 */
|
|
clocks = <&tegra_car 67>, <&tegra_car 124>;
|
|
};
|
|
|
|
i2c@7000d000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "nvidia,tegra20-i2c-dvc";
|
|
reg = <0x7000D000 0x200>;
|
|
interrupts = < 85 >;
|
|
/* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
|
|
clocks = <&tegra_car 47>, <&tegra_car 124>;
|
|
};
|
|
|
|
kbc@7000e200 {
|
|
compatible = "nvidia,tegra20-kbc";
|
|
reg = <0x7000e200 0x0078>;
|
|
};
|
|
|
|
emc@7000f400 {
|
|
#address-cells = < 1 >;
|
|
#size-cells = < 0 >;
|
|
compatible = "nvidia,tegra20-emc";
|
|
reg = <0x7000f400 0x200>;
|
|
};
|
|
|
|
usb@c5000000 {
|
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
|
reg = <0xc5000000 0x4000>;
|
|
interrupts = < 52 >;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car 22>; /* PERIPH_ID_USBD */
|
|
nvidia,has-legacy-mode;
|
|
};
|
|
|
|
usb@c5004000 {
|
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
|
reg = <0xc5004000 0x4000>;
|
|
interrupts = < 53 >;
|
|
phy_type = "ulpi";
|
|
clocks = <&tegra_car 58>; /* PERIPH_ID_USB2 */
|
|
};
|
|
|
|
usb@c5008000 {
|
|
compatible = "nvidia,tegra20-ehci", "usb-ehci";
|
|
reg = <0xc5008000 0x4000>;
|
|
interrupts = < 129 >;
|
|
phy_type = "utmi";
|
|
clocks = <&tegra_car 59>; /* PERIPH_ID_USB3 */
|
|
};
|
|
|
|
sdhci@c8000000 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000000 0x200>;
|
|
interrupts = <0 14 0x04>;
|
|
clocks = <&tegra_car 14>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000200 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000200 0x200>;
|
|
interrupts = <0 15 0x04>;
|
|
clocks = <&tegra_car 9>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000400 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000400 0x200>;
|
|
interrupts = <0 19 0x04>;
|
|
clocks = <&tegra_car 69>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci@c8000600 {
|
|
compatible = "nvidia,tegra20-sdhci";
|
|
reg = <0xc8000600 0x200>;
|
|
interrupts = <0 31 0x04>;
|
|
clocks = <&tegra_car 15>;
|
|
status = "disabled";
|
|
};
|
|
};
|