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6235df946e
IncaIP is a SoC and its specific code should reside in an own SoC subdirectory. Also add -mtune=4kc flag for CPU optimization. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> Cc: Wolfgang Denk <wd@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@pobox.com>
177 lines
6.3 KiB
C
177 lines
6.3 KiB
C
/* incaAscSio.h - (INCA) ASC UART tty driver header */
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#ifndef __INCincaAscSioh
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#define __INCincaAscSioh
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#include <asm/inca-ip.h>
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/* channel operating modes */
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#define ASCOPT_CSIZE 0x00000003
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#define ASCOPT_CS7 0x00000001
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#define ASCOPT_CS8 0x00000002
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#define ASCOPT_PARENB 0x00000004
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#define ASCOPT_STOPB 0x00000008
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#define ASCOPT_PARODD 0x00000010
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#define ASCOPT_CREAD 0x00000020
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#define ASC_OPTIONS (ASCOPT_CREAD | ASCOPT_CS8)
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/* ASC input select (0 or 1) */
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#define CONSOLE_TTY 0
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/* use fractional divider for baudrate settings */
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#define INCAASC_USE_FDV
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#ifdef INCAASC_USE_FDV
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#define INCAASC_FDV_LOW_BAUDRATE 71
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#define INCAASC_FDV_HIGH_BAUDRATE 453
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#endif /*INCAASC_USE_FDV*/
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#define INCAASC_TXFIFO_FL 1
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#define INCAASC_RXFIFO_FL 1
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#define INCAASC_TXFIFO_FULL 16
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/* interrupt lines masks for the ASC device interrupts*/
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/* change these macroses if it's necessary */
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#define INCAASC_IRQ_LINE_ALL 0x000F0000 /* all IRQs */
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#define INCAASC_IRQ_LINE_TIR 0x00010000 /* TIR - Tx */
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#define INCAASC_IRQ_LINE_RIR 0x00020000 /* RIR - Rx */
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#define INCAASC_IRQ_LINE_EIR 0x00040000 /* EIR - Err */
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#define INCAASC_IRQ_LINE_TBIR 0x00080000 /* TBIR - Tx Buf*/
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/* interrupt controller access macros */
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#define ASC_INTERRUPTS_ENABLE(X) \
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*((volatile unsigned int*) INCA_IP_ICU_IM2_IER) |= X;
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#define ASC_INTERRUPTS_DISABLE(X) \
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*((volatile unsigned int*) INCA_IP_ICU_IM2_IER) &= ~X;
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#define ASC_INTERRUPTS_CLEAR(X) \
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*((volatile unsigned int*) INCA_IP_ICU_IM2_ISR) = X;
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/* CLC register's bits and bitfields */
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#define ASCCLC_DISR 0x00000001
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#define ASCCLC_DISS 0x00000002
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#define ASCCLC_RMCMASK 0x0000FF00
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#define ASCCLC_RMCOFFSET 8
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/* CON register's bits and bitfields */
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#define ASCCON_MODEMASK 0x0007
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#define ASCCON_M_8SYNC 0x0
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#define ASCCON_M_8ASYNC 0x1
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#define ASCCON_M_8IRDAASYNC 0x2
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#define ASCCON_M_7ASYNCPAR 0x3
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#define ASCCON_M_9ASYNC 0x4
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#define ASCCON_M_8WAKEUPASYNC 0x5
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#define ASCCON_M_8ASYNCPAR 0x7
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#define ASCCON_STP 0x0008
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#define ASCCON_REN 0x0010
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#define ASCCON_PEN 0x0020
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#define ASCCON_FEN 0x0040
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#define ASCCON_OEN 0x0080
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#define ASCCON_PE 0x0100
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#define ASCCON_FE 0x0200
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#define ASCCON_OE 0x0400
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#define ASCCON_FDE 0x0800
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#define ASCCON_ODD 0x1000
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#define ASCCON_BRS 0x2000
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#define ASCCON_LB 0x4000
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#define ASCCON_R 0x8000
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/* WHBCON register's bits and bitfields */
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#define ASCWHBCON_CLRREN 0x0010
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#define ASCWHBCON_SETREN 0x0020
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#define ASCWHBCON_CLRPE 0x0100
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#define ASCWHBCON_CLRFE 0x0200
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#define ASCWHBCON_CLROE 0x0400
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#define ASCWHBCON_SETPE 0x0800
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#define ASCWHBCON_SETFE 0x1000
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#define ASCWHBCON_SETOE 0x2000
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/* ABCON register's bits and bitfields */
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#define ASCABCON_ABEN 0x0001
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#define ASCABCON_AUREN 0x0002
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#define ASCABCON_ABSTEN 0x0004
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#define ASCABCON_ABDETEN 0x0008
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#define ASCABCON_FCDETEN 0x0010
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#define ASCABCON_EMMASK 0x0300
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#define ASCABCON_EMOFF 8
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#define ASCABCON_EM_DISAB 0x0
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#define ASCABCON_EM_DURAB 0x1
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#define ASCABCON_EM_ALWAYS 0x2
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#define ASCABCON_TXINV 0x0400
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#define ASCABCON_RXINV 0x0800
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/* FDV register mask, offset and bitfields*/
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#define ASCFDV_VALUE_MASK 0x000001FF
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/* WHBABCON register's bits and bitfields */
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#define ASCWHBABCON_SETABEN 0x0001
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#define ASCWHBABCON_CLRABEN 0x0002
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/* ABSTAT register's bits and bitfields */
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#define ASCABSTAT_FCSDET 0x0001
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#define ASCABSTAT_FCCDET 0x0002
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#define ASCABSTAT_SCSDET 0x0004
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#define ASCABSTAT_SCCDET 0x0008
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#define ASCABSTAT_DETWAIT 0x0010
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/* WHBABSTAT register's bits and bitfields */
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#define ASCWHBABSTAT_CLRFCSDET 0x0001
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#define ASCWHBABSTAT_SETFCSDET 0x0002
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#define ASCWHBABSTAT_CLRFCCDET 0x0004
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#define ASCWHBABSTAT_SETFCCDET 0x0008
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#define ASCWHBABSTAT_CLRSCSDET 0x0010
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#define ASCWHBABSTAT_SETSCSDET 0x0020
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#define ASCWHBABSTAT_SETSCCDET 0x0040
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#define ASCWHBABSTAT_CLRSCCDET 0x0080
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#define ASCWHBABSTAT_CLRDETWAIT 0x0100
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#define ASCWHBABSTAT_SETDETWAIT 0x0200
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/* TXFCON register's bits and bitfields */
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#define ASCTXFCON_TXFEN 0x0001
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#define ASCTXFCON_TXFFLU 0x0002
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#define ASCTXFCON_TXTMEN 0x0004
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#define ASCTXFCON_TXFITLMASK 0x3F00
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#define ASCTXFCON_TXFITLOFF 8
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/* RXFCON register's bits and bitfields */
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#define ASCRXFCON_RXFEN 0x0001
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#define ASCRXFCON_RXFFLU 0x0002
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#define ASCRXFCON_RXTMEN 0x0004
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#define ASCRXFCON_RXFITLMASK 0x3F00
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#define ASCRXFCON_RXFITLOFF 8
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/* FSTAT register's bits and bitfields */
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#define ASCFSTAT_RXFFLMASK 0x003F
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#define ASCFSTAT_TXFFLMASK 0x3F00
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#define ASCFSTAT_TXFFLOFF 8
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#define INCAASC_PMU_ENABLE(BIT) *((volatile ulong*)0xBF102000) |= (0x1 << BIT);
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typedef struct /* incaAsc_t */
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{
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volatile unsigned long asc_clc; /*0x0000*/
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volatile unsigned long asc_pisel; /*0x0004*/
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volatile unsigned long asc_rsvd1[2]; /* for mapping */ /*0x0008*/
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volatile unsigned long asc_con; /*0x0010*/
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volatile unsigned long asc_bg; /*0x0014*/
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volatile unsigned long asc_fdv; /*0x0018*/
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volatile unsigned long asc_pmw; /* not used */ /*0x001C*/
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volatile unsigned long asc_tbuf; /*0x0020*/
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volatile unsigned long asc_rbuf; /*0x0024*/
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volatile unsigned long asc_rsvd2[2]; /* for mapping */ /*0x0028*/
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volatile unsigned long asc_abcon; /*0x0030*/
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volatile unsigned long asc_abstat; /* not used */ /*0x0034*/
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volatile unsigned long asc_rsvd3[2]; /* for mapping */ /*0x0038*/
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volatile unsigned long asc_rxfcon; /*0x0040*/
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volatile unsigned long asc_txfcon; /*0x0044*/
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volatile unsigned long asc_fstat; /*0x0048*/
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volatile unsigned long asc_rsvd4; /* for mapping */ /*0x004C*/
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volatile unsigned long asc_whbcon; /*0x0050*/
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volatile unsigned long asc_whbabcon; /*0x0054*/
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volatile unsigned long asc_whbabstat; /* not used */ /*0x0058*/
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} incaAsc_t;
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#endif /* __INCincaAscSioh */
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