mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-20 03:38:43 +00:00
c7de829c79
Add code for AmigaOne board
(preliminary merge to U-Boot, still WIP)
* Patch by Jon Diekema, 12 Nov 2002:
- Adding URL for IEEE OUI lookup
- Making the autoboot #defines dependent on CONFIG_AUTOBOOT_KEYED
being defined.
- In the CONFIG_EXTRA_ENV_SETTINGS #define, the root-on-initrd and
root-on-nfs macros are designed to switch how the default boot
method gets defined.
206 lines
3.3 KiB
C
206 lines
3.3 KiB
C
#include "memio.h"
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#include "articiaS.h"
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#ifndef FALSE
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#define FALSE 0
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#endif
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#ifndef TRUE
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#define TRUE 1
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#endif
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void sm_write_mode(void)
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{
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out_byte(0xA539, 0x00);
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out_byte(0xA53A, 0x03);
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}
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void sm_read_mode(void)
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{
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out_byte(0xA53A, 0x02);
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out_byte(0xA539, 0x02);
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}
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void sm_write_byte(uint8 writeme)
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{
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int i;
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int level;
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out_byte(0xA539, 0x00);
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level = 0;
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for (i=0; i<8; i++)
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{
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if ((writeme & 0x80) == (level<<7))
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{
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/* Bit did not change, rewrite strobe */
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out_byte(0xA539, level | 0x02);
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out_byte(0xA539, level);
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}
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else
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{
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/* Bit changed, set bit, then strobe */
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level = (writeme & 0x80) >> 7;
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out_byte(0xA539, level);
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out_byte(0xA539, level | 0x02);
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out_byte(0xA539, level);
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}
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writeme <<= 1;
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}
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out_byte(0xA539, 0x00);
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}
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uint8 sm_read_byte(void)
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{
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uint8 retme, r;
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int i;
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retme = 0;
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for (i=0; i<8; i++)
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{
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retme <<= 1;
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out_byte(0xA539, 0x00);
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out_byte(0xA539, 0x02);
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r = in_byte(0xA538) & 0x01;
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retme |= r;
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}
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return retme;
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}
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int sm_get_ack(void)
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{
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uint8 r;
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r = in_byte(0xA538);
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if ((r&0x01) == 0) return TRUE;
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else return FALSE;
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}
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void sm_write_ack(void)
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{
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out_byte(0xA539, 0x00);
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out_byte(0xA539, 0x02);
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out_byte(0xA539, 0x00);
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}
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void sm_write_nack(void)
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{
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out_byte(0xA539, 0x01);
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out_byte(0xA539, 0x03);
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out_byte(0xA539, 0x01);
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}
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void sm_send_start(void)
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{
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out_byte(0xA539, 0x03);
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out_byte(0xA539, 0x02);
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}
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void sm_send_stop(void)
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{
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out_byte(0xA539, 0x02);
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out_byte(0xA539, 0x03);
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}
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int sm_read_byte_from_device(uint8 addr, uint8 reg, uint8 *storage)
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{
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// S Addr Wr
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sm_write_mode();
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sm_send_start();
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sm_write_byte((addr<<1));
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// [A]
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sm_read_mode();
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if (sm_get_ack() == FALSE) return FALSE;
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// Comm
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sm_write_mode();
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sm_write_byte(reg);
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// [A]
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sm_read_mode();
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if (sm_get_ack() == FALSE) return FALSE;
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// S Addr Rd
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sm_write_mode();
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sm_send_start();
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sm_write_byte((addr<<1)|1);
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// [A]
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sm_read_mode();
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if (sm_get_ack() == FALSE) return FALSE;
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// [Data]
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*storage = sm_read_byte();
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// NA
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sm_write_mode();
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sm_write_nack();
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sm_send_stop();
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return TRUE;
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}
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void sm_init(void)
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{
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/* Switch to PMC mode */
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pci_write_cfg_byte(0, 0, REG_GROUP, (uint8)(REG_GROUP_SPECIAL|REG_GROUP_POWER));
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/* Set GPIO Base */
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pci_write_cfg_long(0, 0, 0x40, 0xa500);
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/* Enable GPIO */
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pci_write_cfg_byte(0, 0, 0x44, 0x11);
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/* Set both GPIO 0 and 1 as output */
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out_byte(0xA53A, 0x03);
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}
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void sm_term(void)
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{
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/* Switch to normal mode */
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pci_write_cfg_byte(0, 0, REG_GROUP, 0);
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}
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int sm_get_data(uint8 *DataArray, int dimm_socket)
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{
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int j;
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#if 0
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/* Switch to PMC mode */
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pci_write_cfg_byte(0, 0, REG_GROUP, (uint8)(REG_GROUP_SPECIAL|REG_GROUP_POWER));
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/* Set GPIO Base */
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pci_write_cfg_long(0, 0, 0x40, 0xa500);
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/* Enable GPIO */
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pci_write_cfg_byte(0, 0, 0x44, 0x11);
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/* Set both GPIO 0 and 1 as output */
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out_byte(0xA53A, 0x03);
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#endif
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sm_init();
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/* Start reading the rom */
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j = 0;
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do
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{
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if (sm_read_byte_from_device(dimm_socket, (uint8)j, DataArray) == FALSE)
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{
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sm_term();
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return FALSE;
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}
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DataArray++;
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j++;
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} while (j < 128);
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sm_term();
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return TRUE;
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}
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