mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-16 00:03:24 +00:00
fa9ccff835
Update PBI command in pbi_cfg files to keep register bit to default reset value while configuring CPC as SRAM Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
36 lines
784 B
INI
36 lines
784 B
INI
#PBI commands
|
|
#Software Workaround for errata A-007662 to train PCIe2 controller in Gen2 speed
|
|
09250100 00000400
|
|
09250108 00002000
|
|
#Software Workaround for errata A-008007 to reset PVR register
|
|
09000010 0000000b
|
|
09000014 c0000000
|
|
09000018 81d00017
|
|
89020400 a1000000
|
|
091380c0 000f0000
|
|
89020400 00000000
|
|
#Initialize CPC1
|
|
09010000 00200400
|
|
09138000 00000000
|
|
091380c0 00000100
|
|
#Configure CPC1 as 256KB SRAM
|
|
09010100 00000000
|
|
09010104 fffc0007
|
|
09010f00 081e000d
|
|
09010000 80000000
|
|
#Configure LAW for CPC1
|
|
09000cd0 00000000
|
|
09000cd4 fffc0000
|
|
09000cd8 81000011
|
|
#Configure alternate space
|
|
09000010 00000000
|
|
09000014 ff000000
|
|
09000018 81000000
|
|
#Configure SPI controller
|
|
09110000 80000403
|
|
09110020 2d170008
|
|
09110024 00100008
|
|
09110028 00100008
|
|
0911002c 00100008
|
|
#Flush PBL data
|
|
091380c0 000FFFFF
|