mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 19:28:36 +00:00
8bde7f776c
- remove trailing white space, trailing empty lines, C++ comments, etc.
- split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c)
* Patches by Kenneth Johansson, 25 Jun 2003:
- major rework of command structure
(work done mostly by Michal Cendrowski and Joakim Kristiansen)
55 lines
2.4 KiB
ArmAsm
55 lines
2.4 KiB
ArmAsm
/*------------------------------------------------------------------------------+ */
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/* */
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/* This source code has been made available to you by IBM on an AS-IS */
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/* basis. Anyone receiving this source is licensed under IBM */
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/* copyrights to use it in any way he or she deems fit, including */
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/* copying it, modifying it, compiling it, and redistributing it either */
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/* with or without modifications. No license under IBM patents or */
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/* patent applications is to be implied by the copyright license. */
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/* */
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/* Any user of this software should understand that IBM cannot provide */
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/* technical support for this software and will not be responsible for */
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/* any consequences resulting from the use of this software. */
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/* */
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/* Any person who transfers this source code or any derivative work */
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/* must include the IBM copyright notice, this paragraph, and the */
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/* preceding two paragraphs in the transferred software. */
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/* */
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/* COPYRIGHT I B M CORPORATION 1995 */
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/* LICENSED MATERIAL - PROGRAM PROPERTY OF I B M */
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/*------------------------------------------------------------------------------- */
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/*----------------------------------------------------------------------------- */
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/* Function: ext_bus_cntlr_init */
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/* Description: Initializes the External Bus Controller for the external */
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/* peripherals. IMPORTANT: For pass1 this code must run from */
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/* cache since you can not reliably change a peripheral banks */
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/* timing register (pbxap) while running code from that bank. */
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/* For ex., since we are running from ROM on bank 0, we can NOT */
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/* execute the code that modifies bank 0 timings from ROM, so */
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/* we run it from cache. */
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/* Bank 0 - Flash and SRAM */
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/* Bank 1 - NVRAM/RTC */
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/* Bank 2 - Keyboard/Mouse controller */
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/* Bank 3 - IR controller */
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/* Bank 4 - not used */
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/* Bank 5 - not used */
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/* Bank 6 - not used */
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/* Bank 7 - FPGA registers */
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/*----------------------------------------------------------------------------- */
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#include <ppc4xx.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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/*----------------------------------------------------------------------------- */
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/* Function: sdram_init */
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/* Description: Dummy implementation here - done in C later */
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/*----------------------------------------------------------------------------- */
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.globl sdram_init
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sdram_init:
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blr
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