mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-25 06:00:43 +00:00
efb5dab7ba
As this symbol can either be a fixed value or the function get_board_ddr_clk, migration is tricky. Introduce a choice of DYNAMIC or STATIC_DDR_CLK_FREQ. If DYNAMIC, we continue to use the board defined get_board_ddr_clk function. If STATIC, set CONFIG_DDR_CLK_FREQ to that value and now include/clock_legacy.h contains the function prototype or defines get_board_ddr_clk() to that static value. Update callers to test for DYNAMIC or STATIC. Signed-off-by: Tom Rini <trini@konsulko.com>
92 lines
2.1 KiB
Text
92 lines
2.1 KiB
Text
CONFIG_PPC=y
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CONFIG_SYS_TEXT_BASE=0x11001000
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CONFIG_SPL_LIBCOMMON_SUPPORT=y
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CONFIG_SPL_LIBGENERIC_SUPPORT=y
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0x100000
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CONFIG_ENV_SECT_SIZE=0x10000
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CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc"
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CONFIG_SPL_TEXT_BASE=0xf8f81000
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CONFIG_SPL_SERIAL_SUPPORT=y
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CONFIG_SPL=y
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CONFIG_SPL_SPI_FLASH_SUPPORT=y
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CONFIG_SPL_SPI_SUPPORT=y
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CONFIG_MPC85xx=y
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# CONFIG_CMD_ERRATA is not set
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CONFIG_TARGET_P1020RDB_PC=y
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CONFIG_FIT=y
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CONFIG_FIT_VERBOSE=y
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CONFIG_OF_BOARD_SETUP=y
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CONFIG_OF_STDOUT_VIA_ALIAS=y
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CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
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CONFIG_BOOTDELAY=10
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CONFIG_BOARD_EARLY_INIT_F=y
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CONFIG_BOARD_EARLY_INIT_R=y
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# CONFIG_MISC_INIT_R is not set
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# CONFIG_SPL_FRAMEWORK is not set
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CONFIG_SPL_SPI_BOOT=y
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CONFIG_SPL_ENV_SUPPORT=y
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CONFIG_SPL_I2C=y
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CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT=y
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CONFIG_HUSH_PARSER=y
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# CONFIG_AUTO_COMPLETE is not set
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CONFIG_CMD_IMLS=y
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CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3
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CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_MP=y
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# CONFIG_CMD_HASH is not set
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_FAT=y
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_SPI_FLASH=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_DM=y
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CONFIG_DDR_CLK_FREQ=66666666
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CONFIG_DM_I2C=y
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CONFIG_SPL_SYS_I2C_LEGACY=y
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CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
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CONFIG_SYS_I2C_FSL=y
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CONFIG_SYS_FSL_I2C_OFFSET=0x3000
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CONFIG_SYS_FSL_HAS_I2C2_OFFSET=y
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CONFIG_SYS_FSL_I2C2_OFFSET=0x3100
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CONFIG_SYS_I2C_EEPROM_ADDR=0x52
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CONFIG_FSL_ESDHC=y
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CONFIG_MTD=y
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CONFIG_MTD_NOR_FLASH=y
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CONFIG_FLASH_CFI_DRIVER=y
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CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
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CONFIG_SYS_FLASH_CFI=y
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CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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CONFIG_SF_DEFAULT_SPEED=10000000
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHY_ATHEROS=y
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CONFIG_PHY_BROADCOM=y
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CONFIG_PHY_DAVICOM=y
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CONFIG_PHY_LXT=y
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CONFIG_PHY_MARVELL=y
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CONFIG_PHY_NATSEMI=y
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CONFIG_PHY_REALTEK=y
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CONFIG_PHY_SMSC=y
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CONFIG_PHY_VITESSE=y
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CONFIG_PHY_FIXED=y
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CONFIG_DM_ETH=y
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CONFIG_DM_MDIO=y
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CONFIG_PHY_GIGE=y
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CONFIG_E1000=y
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CONFIG_MII=y
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CONFIG_TSEC_ENET=y
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CONFIG_PCIE_FSL=y
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CONFIG_DM_RTC=y
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CONFIG_SYS_NS16550=y
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CONFIG_SPI=y
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CONFIG_DM_SPI=y
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CONFIG_FSL_ESPI=y
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CONFIG_USB=y
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CONFIG_USB_STORAGE=y
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