u-boot/arch/arm/mach-mvebu/arm64-common.c
Stefan Roese 21b29fc64e arm64: mvebu: Add basic support for the Marvell Armada 7K/8K SoC
Compared to the Armada 3700, the Armada 7K and 8K are much more on the
high-end side: they use a dual Cortex-A72 or a quad Cortex-A72, as
opposed to the Cortex-A53 for the Armada 3700.

The Armada 7K and 8K also use a fairly unique architecture, internally
they are composed of several components:

- One AP (Application Processor), which contains the processor itself
  and a few core hardware blocks. The AP used in the Armada 7K and 8K
  is called AP806, and is available in two configurations:
  dual Cortex-A72 and quad Cortex-A72.
- One or two CP (Communication Processor), which contain most of the I/O
  interfaces (SATA, PCIe, Ethernet, etc.). The 7K family chips have one
  CP, while the 8K family chips integrate two CPs, providing two times
  the number of I/O interfaces available in the CP.
  The CP used in the 7K and 8K is called CP110.

All in all, this gives the following combinations:

- Armada 7020, which is a dual Cortex-A72 with one CP
- Armada 7040, which is a quad Cortex-A72 with one CP
- Armada 8020, which is a dual Cortex-A72 with two CPs
- Armada 8040, which is a quad Cortex-A72 with two CPs

This patch adds basic support for this ARMv8 based SoC into U-Boot.
Future patches will integrate other device drivers and board support,
starting with the Marvell DB-88F7040 development board.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Neta Zur Hershkovits <neta@marvell.com>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Omri Itach <omrii@marvell.com>
Cc: Igal Liberman <igall@marvell.com>
Cc: Haim Boot <hayim@marvell.com>
Cc: Hanna Hawa <hannah@marvell.com>
2016-09-27 17:29:54 +02:00

124 lines
2.4 KiB
C

/*
* Copyright (C) 2016 Stefan Roese <sr@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <dm.h>
#include <fdtdec.h>
#include <libfdt.h>
#include <asm/io.h>
#include <asm/system.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>
#include <asm/armv8/mmu.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* On ARMv8, MBus is not configured in U-Boot. To enable compilation
* of the already implemented drivers, lets add a dummy version of
* this function so that linking does not fail.
*/
const struct mbus_dram_target_info *mvebu_mbus_dram_info(void)
{
return NULL;
}
/* DRAM init code ... */
static const void *get_memory_reg_prop(const void *fdt, int *lenp)
{
int offset;
offset = fdt_path_offset(fdt, "/memory");
if (offset < 0)
return NULL;
return fdt_getprop(fdt, offset, "reg", lenp);
}
int dram_init(void)
{
const void *fdt = gd->fdt_blob;
const fdt32_t *val;
int ac, sc, len;
ac = fdt_address_cells(fdt, 0);
sc = fdt_size_cells(fdt, 0);
if (ac < 0 || sc < 1 || sc > 2) {
printf("invalid address/size cells\n");
return -EINVAL;
}
val = get_memory_reg_prop(fdt, &len);
if (len / sizeof(*val) < ac + sc)
return -EINVAL;
val += ac;
gd->ram_size = fdtdec_get_number(val, sc);
debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size);
return 0;
}
void dram_init_banksize(void)
{
const void *fdt = gd->fdt_blob;
const fdt32_t *val;
int ac, sc, cells, len, i;
val = get_memory_reg_prop(fdt, &len);
if (len < 0)
return;
ac = fdt_address_cells(fdt, 0);
sc = fdt_size_cells(fdt, 0);
if (ac < 1 || sc > 2 || sc < 1 || sc > 2) {
printf("invalid address/size cells\n");
return;
}
cells = ac + sc;
len /= sizeof(*val);
for (i = 0; i < CONFIG_NR_DRAM_BANKS && len >= cells;
i++, len -= cells) {
gd->bd->bi_dram[i].start = fdtdec_get_number(val, ac);
val += ac;
gd->bd->bi_dram[i].size = fdtdec_get_number(val, sc);
val += sc;
debug("DRAM bank %d: start = %08lx, size = %08lx\n",
i, (unsigned long)gd->bd->bi_dram[i].start,
(unsigned long)gd->bd->bi_dram[i].size);
}
}
int arch_cpu_init(void)
{
/* Nothing to do (yet) */
return 0;
}
int arch_early_init_r(void)
{
struct udevice *dev;
int ret;
/* Call the comphy code via the MISC uclass driver */
ret = uclass_get_device(UCLASS_MISC, 0, &dev);
if (ret) {
debug("COMPHY init failed: %d\n", ret);
return -ENODEV;
}
/* Cause the SATA device to do its early init */
uclass_first_device(UCLASS_AHCI, &dev);
return 0;
}