mirror of
https://github.com/AsahiLinux/u-boot
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7ffe3cd62e
Since CONFIG_OF_BOARD_SETUP depends on CONFIG_OF_LIBFDT:
config OF_BOARD_SETUP
bool "Set up board-specific details in device tree before boot"
depends on OF_LIBFDT
...
remove superfluous tests of CONFIG_OF_LIBFDT when testing for
CONFIG_OF_BOARD_SETUP.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
[trini: Typo fix: s/ifdefi/ifdef/]
Signed-off-by: Tom Rini <trini@konsulko.com>
321 lines
7.2 KiB
C
321 lines
7.2 KiB
C
/*
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* (C) Copyright 2000-2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
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*
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* written or collected and sometimes rewritten by
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* Magnus Damm <damm@bitsmart.com>
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*
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* modified by
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* Wolfgang Denk <wd@denx.de>
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*
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* modified for 8260 by
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* Murray Jensen <Murray.Jensen@cmst.csiro.au>
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*
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* added 8260 masks by
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* Marius Groeger <mag@sysgo.de>
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*
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* added HiP7 (824x/827x/8280) processors support by
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* Yuli Barcohen <yuli@arabellasw.com>
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <command.h>
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#include <mpc8260.h>
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#include <netdev.h>
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#include <asm/processor.h>
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#include <asm/cpm_8260.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#include <fdt_support.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_GET_CPU_STR_F)
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extern int get_cpu_str_f (char *buf);
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#endif
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int checkcpu (void)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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ulong clock = gd->cpu_clk;
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uint pvr = get_pvr ();
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uint immr, rev, m, k;
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char buf[32];
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puts ("CPU: ");
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switch (pvr) {
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case PVR_8260:
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case PVR_8260_HIP3:
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k = 3;
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break;
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case PVR_8260_HIP4:
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k = 4;
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break;
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case PVR_8260_HIP7R1:
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case PVR_8260_HIP7RA:
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case PVR_8260_HIP7:
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k = 7;
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break;
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default:
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return -1; /* whoops! not an MPC8260 */
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}
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rev = pvr & 0xff;
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immr = immap->im_memctl.memc_immr;
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if ((immr & IMMR_ISB_MSK) != CONFIG_SYS_IMMR)
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return -1; /* whoops! someone moved the IMMR */
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#if defined(CONFIG_GET_CPU_STR_F)
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get_cpu_str_f (buf);
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printf ("%s (HiP%d Rev %02x, Mask ", buf, k, rev);
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#else
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printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
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#endif
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/*
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* the bottom 16 bits of the immr are the Part Number and Mask Number
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* (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
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* RISC Microcode Revision Number (13-10).
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* For the 8260, Motorola doesn't include the Microcode Revision
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* in the mask.
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*/
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m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
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k = immap->im_dprambase16[PROFF_REVNUM / sizeof(u16)];
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switch (m) {
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case 0x0000:
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puts ("0.2 2J24M");
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break;
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case 0x0010:
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puts ("A.0 K22A");
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break;
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case 0x0011:
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puts ("A.1 1K22A-XC");
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break;
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case 0x0001:
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puts ("B.1 1K23A");
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break;
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case 0x0021:
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puts ("B.2 2K23A-XC");
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break;
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case 0x0023:
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puts ("B.3 3K23A");
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break;
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case 0x0024:
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puts ("C.2 6K23A");
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break;
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case 0x0060:
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puts ("A.0(A) 2K25A");
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break;
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case 0x0062:
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puts ("B.1 4K25A");
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break;
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case 0x0064:
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puts ("C.0 5K25A");
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break;
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case 0x0A00:
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puts ("0.0 0K49M");
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break;
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case 0x0A01:
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puts ("0.1 1K49M");
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break;
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case 0x0A10:
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puts ("1.0 1K49M");
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break;
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case 0x0C00:
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puts ("0.0 0K50M");
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break;
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case 0x0C10:
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puts ("1.0 1K50M");
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break;
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case 0x0D00:
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puts ("0.0 0K50M");
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break;
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case 0x0D10:
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puts ("1.0 1K50M");
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break;
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default:
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printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
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break;
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}
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printf (") at %s MHz\n", strmhz (buf, clock));
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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/* configures a UPM by writing into the UPM RAM array */
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/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
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/* NOTE: the physical address chosen must not overlap into any other area */
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/* mapped by the memory controller because bank 11 has the lowest priority */
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void upmconfig (uint upm, uint * table, uint size)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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volatile memctl8260_t *memctl = &immap->im_memctl;
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volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */
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uint i;
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/* first set up bank 11 to reference the correct UPM at a dummy address */
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memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */
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switch (upm) {
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case UPMA:
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memctl->memc_br11 =
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((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
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BRx_V;
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memctl->memc_mamr = MxMR_OP_WARR;
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break;
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case UPMB:
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memctl->memc_br11 =
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((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
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BRx_V;
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memctl->memc_mbmr = MxMR_OP_WARR;
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break;
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case UPMC:
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memctl->memc_br11 =
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((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
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BRx_V;
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memctl->memc_mcmr = MxMR_OP_WARR;
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break;
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default:
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panic ("upmconfig passed invalid UPM number (%u)\n", upm);
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break;
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}
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/*
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* at this point, the dummy address is set up to access the selected UPM,
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* the MAD pointer is zero, and the MxMR OP is set for writing to RAM
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*
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* now we simply load the mdr with each word and poke the dummy address.
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* the MAD is incremented on each access.
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*/
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for (i = 0; i < size; i++) {
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memctl->memc_mdr = table[i];
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*dummy = 0;
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}
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/* now kill bank 11 */
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memctl->memc_br11 = 0;
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}
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/* ------------------------------------------------------------------------- */
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#if !defined(CONFIG_HAVE_OWN_RESET)
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int
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do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
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{
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ulong msr, addr;
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */
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/* Interrupts and MMU off */
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__asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
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msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
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__asm__ __volatile__ ("mtmsr %0"::"r" (msr));
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/*
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* Trying to execute the next instruction at a non-existing address
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* should cause a machine check, resulting in reset
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*/
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#ifdef CONFIG_SYS_RESET_ADDRESS
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addr = CONFIG_SYS_RESET_ADDRESS;
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#else
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/*
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* note: when CONFIG_SYS_MONITOR_BASE points to a RAM address, CONFIG_SYS_MONITOR_BASE
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* - sizeof (ulong) is usually a valid address. Better pick an address
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* known to be invalid on your system and assign it to CONFIG_SYS_RESET_ADDRESS.
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*/
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addr = CONFIG_SYS_MONITOR_BASE - sizeof (ulong);
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#endif
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((void (*)(void)) addr) ();
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return 1;
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}
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#endif /* CONFIG_HAVE_OWN_RESET */
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/* ------------------------------------------------------------------------- */
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/*
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* Get timebase clock frequency (like cpu_clk in Hz)
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*
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*/
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unsigned long get_tbclk (void)
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{
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ulong tbclk;
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tbclk = (gd->bus_clk + 3L) / 4L;
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return (tbclk);
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}
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/* ------------------------------------------------------------------------- */
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#if defined(CONFIG_WATCHDOG)
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void watchdog_reset (void)
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{
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int re_enable = disable_interrupts ();
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reset_8260_watchdog ((immap_t *) CONFIG_SYS_IMMR);
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if (re_enable)
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enable_interrupts ();
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}
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#endif /* CONFIG_WATCHDOG */
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_OF_BOARD_SETUP
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void ft_cpu_setup (void *blob, bd_t *bd)
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{
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#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
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defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3)
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fdt_fixup_ethernet(blob);
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#endif
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do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
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"clock-frequency", bd->bi_brgfreq, 1);
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do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
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"bus-frequency", bd->bi_busfreq, 1);
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do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
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"timebase-frequency", OF_TBCLK, 1);
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do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
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"clock-frequency", bd->bi_intfreq, 1);
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fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
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}
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#endif /* CONFIG_OF_BOARD_SETUP */
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/*
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* Initializes on-chip ethernet controllers.
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* to override, implement board_eth_init()
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*/
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int cpu_eth_init(bd_t *bis)
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{
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#if defined(CONFIG_ETHER_ON_FCC)
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fec_initialize(bis);
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#endif
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#if defined(CONFIG_ETHER_ON_SCC)
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mpc82xx_scc_enet_initialize(bis);
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#endif
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return 0;
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}
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