mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 03:08:31 +00:00
ef331e3685
Commit 1416e2d225 ("armv8: make SPL exception vectors optional") had a
typo in it which effectively disabled exception handling in SPL code always.
Since nobody complained, I guess we may as well disable exception handling
in SPL always by default.
So fix the bug to make the config option effective, but disable exception
handling in SPL by default. This gets us to the same functionality as before
by default, but with much less code included in the binary.
Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
374 lines
8.1 KiB
ArmAsm
374 lines
8.1 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013
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* David Feng <fenghua@phytium.com.cn>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <linux/linkage.h>
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#include <asm/macro.h>
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#include <asm/armv8/mmu.h>
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/*************************************************************************
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*
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* Startup Code (reset vector)
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*
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*************************************************************************/
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.globl _start
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_start:
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#if defined(LINUX_KERNEL_IMAGE_HEADER)
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#include <asm/boot0-linux-kernel-header.h>
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#elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
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/*
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* Various SoCs need something special and SoC-specific up front in
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* order to boot, allow them to set that in their boot0.h file and then
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* use it here.
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*/
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#include <asm/arch/boot0.h>
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#else
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b reset
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#endif
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.align 3
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.globl _TEXT_BASE
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_TEXT_BASE:
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.quad CONFIG_SYS_TEXT_BASE
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/*
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* These are defined in the linker script.
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*/
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.globl _end_ofs
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_end_ofs:
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.quad _end - _start
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.globl _bss_start_ofs
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_bss_start_ofs:
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.quad __bss_start - _start
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.globl _bss_end_ofs
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_bss_end_ofs:
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.quad __bss_end - _start
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reset:
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/* Allow the board to save important registers */
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b save_boot_params
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.globl save_boot_params_ret
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save_boot_params_ret:
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#if CONFIG_POSITION_INDEPENDENT
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/*
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* Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
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* executed at a different address than it was linked at.
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*/
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pie_fixup:
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adr x0, _start /* x0 <- Runtime value of _start */
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ldr x1, _TEXT_BASE /* x1 <- Linked value of _start */
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sub x9, x0, x1 /* x9 <- Run-vs-link offset */
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adr x2, __rel_dyn_start /* x2 <- Runtime &__rel_dyn_start */
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adr x3, __rel_dyn_end /* x3 <- Runtime &__rel_dyn_end */
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pie_fix_loop:
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ldp x0, x1, [x2], #16 /* (x0, x1) <- (Link location, fixup) */
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ldr x4, [x2], #8 /* x4 <- addend */
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cmp w1, #1027 /* relative fixup? */
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bne pie_skip_reloc
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/* relative fix: store addend plus offset at dest location */
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add x0, x0, x9
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add x4, x4, x9
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str x4, [x0]
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pie_skip_reloc:
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cmp x2, x3
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b.lo pie_fix_loop
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pie_fixup_done:
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#endif
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#ifdef CONFIG_SYS_RESET_SCTRL
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bl reset_sctrl
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#endif
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#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
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.macro set_vbar, regname, reg
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msr \regname, \reg
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.endm
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adr x0, vectors
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#else
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.macro set_vbar, regname, reg
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.endm
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#endif
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/*
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* Could be EL3/EL2/EL1, Initial State:
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* Little Endian, MMU Disabled, i/dCache Disabled
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*/
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switch_el x1, 3f, 2f, 1f
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3: set_vbar vbar_el3, x0
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mrs x0, scr_el3
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orr x0, x0, #0xf /* SCR_EL3.NS|IRQ|FIQ|EA */
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msr scr_el3, x0
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msr cptr_el3, xzr /* Enable FP/SIMD */
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#ifdef COUNTER_FREQUENCY
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ldr x0, =COUNTER_FREQUENCY
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msr cntfrq_el0, x0 /* Initialize CNTFRQ */
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#endif
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b 0f
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2: set_vbar vbar_el2, x0
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mov x0, #0x33ff
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msr cptr_el2, x0 /* Enable FP/SIMD */
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b 0f
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1: set_vbar vbar_el1, x0
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mov x0, #3 << 20
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msr cpacr_el1, x0 /* Enable FP/SIMD */
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0:
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/*
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* Enable SMPEN bit for coherency.
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* This register is not architectural but at the moment
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* this bit should be set for A53/A57/A72.
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*/
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#ifdef CONFIG_ARMV8_SET_SMPEN
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switch_el x1, 3f, 1f, 1f
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3:
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mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
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orr x0, x0, #0x40
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msr S3_1_c15_c2_1, x0
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1:
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#endif
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/* Apply ARM core specific erratas */
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bl apply_core_errata
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/*
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* Cache/BPB/TLB Invalidate
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* i-cache is invalidated before enabled in icache_enable()
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* tlb is invalidated before mmu is enabled in dcache_enable()
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* d-cache is invalidated before enabled in dcache_enable()
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*/
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/* Processor specific initialization */
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bl lowlevel_init
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#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
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branch_if_master x0, x1, master_cpu
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b spin_table_secondary_jump
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/* never return */
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#elif defined(CONFIG_ARMV8_MULTIENTRY)
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branch_if_master x0, x1, master_cpu
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/*
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* Slave CPUs
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*/
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slave_cpu:
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wfe
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ldr x1, =CPU_RELEASE_ADDR
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ldr x0, [x1]
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cbz x0, slave_cpu
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br x0 /* branch to the given address */
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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master_cpu:
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bl _main
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#ifdef CONFIG_SYS_RESET_SCTRL
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reset_sctrl:
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switch_el x1, 3f, 2f, 1f
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3:
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mrs x0, sctlr_el3
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b 0f
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2:
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mrs x0, sctlr_el2
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b 0f
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1:
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mrs x0, sctlr_el1
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0:
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ldr x1, =0xfdfffffa
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and x0, x0, x1
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switch_el x1, 6f, 5f, 4f
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6:
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msr sctlr_el3, x0
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b 7f
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5:
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msr sctlr_el2, x0
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b 7f
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4:
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msr sctlr_el1, x0
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7:
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dsb sy
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isb
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b __asm_invalidate_tlb_all
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ret
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#endif
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/*-----------------------------------------------------------------------*/
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WEAK(apply_core_errata)
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mov x29, lr /* Save LR */
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/* For now, we support Cortex-A53, Cortex-A57 specific errata */
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/* Check if we are running on a Cortex-A53 core */
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branch_if_a53_core x0, apply_a53_core_errata
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/* Check if we are running on a Cortex-A57 core */
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branch_if_a57_core x0, apply_a57_core_errata
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0:
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mov lr, x29 /* Restore LR */
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ret
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apply_a53_core_errata:
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#ifdef CONFIG_ARM_ERRATA_855873
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mrs x0, midr_el1
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tst x0, #(0xf << 20)
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b.ne 0b
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mrs x0, midr_el1
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and x0, x0, #0xf
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cmp x0, #3
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b.lt 0b
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* Enable data cache clean as data cache clean/invalidate */
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orr x0, x0, #1 << 44
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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#endif
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b 0b
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apply_a57_core_errata:
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#ifdef CONFIG_ARM_ERRATA_828024
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* Disable non-allocate hint of w-b-n-a memory type */
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orr x0, x0, #1 << 49
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/* Disable write streaming no L1-allocate threshold */
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orr x0, x0, #3 << 25
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/* Disable write streaming no-allocate threshold */
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orr x0, x0, #3 << 27
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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#endif
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#ifdef CONFIG_ARM_ERRATA_826974
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* Disable speculative load execution ahead of a DMB */
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orr x0, x0, #1 << 59
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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#endif
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#ifdef CONFIG_ARM_ERRATA_833471
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* FPSCR write flush.
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* Note that in some cases where a flush is unnecessary this
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could impact performance. */
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orr x0, x0, #1 << 38
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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#endif
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#ifdef CONFIG_ARM_ERRATA_829520
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* Disable Indirect Predictor bit will prevent this erratum
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from occurring
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* Note that in some cases where a flush is unnecessary this
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could impact performance. */
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orr x0, x0, #1 << 4
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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#endif
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#ifdef CONFIG_ARM_ERRATA_833069
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mrs x0, S3_1_c15_c2_0 /* cpuactlr_el1 */
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/* Disable Enable Invalidates of BTB bit */
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and x0, x0, #0xE
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msr S3_1_c15_c2_0, x0 /* cpuactlr_el1 */
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#endif
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b 0b
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ENDPROC(apply_core_errata)
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/*-----------------------------------------------------------------------*/
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WEAK(lowlevel_init)
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mov x29, lr /* Save LR */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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branch_if_slave x0, 1f
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ldr x0, =GICD_BASE
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bl gic_init_secure
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1:
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#if defined(CONFIG_GICV3)
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ldr x0, =GICR_BASE
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bl gic_init_secure_percpu
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#elif defined(CONFIG_GICV2)
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ldr x0, =GICD_BASE
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ldr x1, =GICC_BASE
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bl gic_init_secure_percpu
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#endif
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#endif
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#ifdef CONFIG_ARMV8_MULTIENTRY
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branch_if_master x0, x1, 2f
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/*
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* Slave should wait for master clearing spin table.
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* This sync prevent salves observing incorrect
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* value of spin table and jumping to wrong place.
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*/
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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#ifdef CONFIG_GICV2
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ldr x0, =GICC_BASE
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#endif
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bl gic_wait_for_interrupt
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#endif
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/*
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* All slaves will enter EL2 and optionally EL1.
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*/
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adr x4, lowlevel_in_el2
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ldr x5, =ES_TO_AARCH64
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bl armv8_switch_to_el2
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lowlevel_in_el2:
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#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
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adr x4, lowlevel_in_el1
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ldr x5, =ES_TO_AARCH64
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bl armv8_switch_to_el1
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lowlevel_in_el1:
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#endif
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#endif /* CONFIG_ARMV8_MULTIENTRY */
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2:
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mov lr, x29 /* Restore LR */
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ret
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ENDPROC(lowlevel_init)
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WEAK(smp_kick_all_cpus)
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/* Kick secondary cpus up by SGI 0 interrupt */
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#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
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ldr x0, =GICD_BASE
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b gic_kick_secondary_cpus
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#endif
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ret
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ENDPROC(smp_kick_all_cpus)
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/*-----------------------------------------------------------------------*/
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ENTRY(c_runtime_cpu_setup)
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#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
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/* Relocate vBAR */
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adr x0, vectors
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switch_el x1, 3f, 2f, 1f
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3: msr vbar_el3, x0
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b 0f
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2: msr vbar_el2, x0
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b 0f
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1: msr vbar_el1, x0
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0:
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#endif
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ret
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ENDPROC(c_runtime_cpu_setup)
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WEAK(save_boot_params)
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b save_boot_params_ret /* back to my caller */
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ENDPROC(save_boot_params)
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