mirror of
https://github.com/AsahiLinux/u-boot
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165 lines
4.4 KiB
C
165 lines
4.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the Freescale i.MX7D SABRESD board.
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*/
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#ifndef __MX7D_SABRESD_CONFIG_H
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#define __MX7D_SABRESD_CONFIG_H
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#include "mx7_common.h"
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#define PHYS_SDRAM_SIZE SZ_1G
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#define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
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/* MMC Config*/
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#define CONFIG_SYS_FSL_ESDHC_ADDR 0
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/* I2C configs */
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_SPEED 100000
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#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
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#ifdef CONFIG_IMX_BOOTAUX
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/* Set to QSPI1 A flash at default */
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#define CONFIG_SYS_AUXCORE_BOOTDATA 0x60000000
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#define UPDATE_M4_ENV \
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"m4image=m4_qspi.bin\0" \
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"loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
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"update_m4_from_sd=" \
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"if sf probe 0:0; then " \
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"if run loadm4image; then " \
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"setexpr fw_sz ${filesize} + 0xffff; " \
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"setexpr fw_sz ${fw_sz} / 0x10000; " \
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"setexpr fw_sz ${fw_sz} * 0x10000; " \
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"sf erase 0x0 ${fw_sz}; " \
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"sf write ${loadaddr} 0x0 ${filesize}; " \
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"fi; " \
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"fi\0" \
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"m4boot=sf probe 0:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
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#else
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#define UPDATE_M4_ENV ""
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#endif
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#define CONFIG_MFG_ENV_SETTINGS \
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"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
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"rdinit=/linuxrc " \
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"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
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"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
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"g_mass_storage.iSerialNumber=\"\" "\
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"clk_ignore_unused "\
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"\0" \
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"initrd_addr=0x83800000\0" \
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"initrd_high=0xffffffff\0" \
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"bootcmd_mfg=run mfgtool_args;bootz ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
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#define CONFIG_DFU_ENV_SETTINGS \
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"dfu_alt_info=image raw 0 0x800000;"\
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"u-boot raw 0 0x4000;"\
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"bootimg part 0 1;"\
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"rootfs part 0 2\0" \
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#define CONFIG_EXTRA_ENV_SETTINGS \
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UPDATE_M4_ENV \
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CONFIG_MFG_ENV_SETTINGS \
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CONFIG_DFU_ENV_SETTINGS \
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"script=boot.scr\0" \
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"image=zImage\0" \
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"console=ttymxc0\0" \
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"fdt_high=0xffffffff\0" \
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"finduuid=part uuid mmc 0:1 uuid\0" \
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"initrd_high=0xffffffff\0" \
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"fdtfile=imx7d-sdb.dtb\0" \
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"fdt_addr=0x83000000\0" \
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"fdt_addr_r=0x83000000\0" \
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"kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
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"pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
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"ramdisk_addr_r=0x83000000\0" \
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"ramdiskaddr=0x83000000\0" \
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"scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
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"videomode=video=ctfb:x:480,y:272,depth:24,pclk:108695,le:8,ri:4,up:2,lo:4,hs:41,vs:10,sync:0,vmode:0\0" \
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BOOTENV
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#define BOOT_TARGET_DEVICES(func) \
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func(MMC, mmc, 0) \
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func(DHCP, dhcp, na) \
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func(PXE, pxe, na)
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#include <config_distro_bootcmd.h>
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x20000000)
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#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
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#define CONFIG_SYS_HZ 1000
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/* Physical Memory Map */
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#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
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#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
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#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
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#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
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#define CONFIG_SYS_INIT_SP_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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#define CONFIG_SYS_INIT_SP_ADDR \
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(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
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/* environment organization */
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/*
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* If want to use nand, define CONFIG_NAND_MXS and rework board
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* to support nand, since emmc has pin conflicts with nand
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*/
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#ifdef CONFIG_NAND_MXS
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/* NAND stuff */
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* DMA stuff, needed for GPMI/MXS NAND support */
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#endif
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#ifdef CONFIG_NAND_MXS
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#define CONFIG_SYS_FSL_USDHC_NUM 1
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#else
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#endif
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#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
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#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
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/* USB Configs */
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_IMX_THERMAL
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#define CONFIG_USBD_HS
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#ifdef CONFIG_VIDEO
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#define CONFIG_VIDEO_MXS
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#define CONFIG_VIDEO_LOGO
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#define CONFIG_SPLASH_SCREEN
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#define CONFIG_SPLASH_SCREEN_ALIGN
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#define CONFIG_BMP_16BPP
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_VIDEO_BMP_LOGO
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#endif
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#ifdef CONFIG_FSL_QSPI
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#define CONFIG_SYS_FSL_QSPI_AHB
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#define FSL_QSPI_FLASH_NUM 1
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#define FSL_QSPI_FLASH_SIZE SZ_64M
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#define QSPI0_BASE_ADDR QSPI1_IPS_BASE_ADDR
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#define QSPI0_AMBA_BASE QSPI0_ARB_BASE_ADDR
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#endif
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#endif /* __CONFIG_H */
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