u-boot/arch/x86/cpu/baytrail
Andrew Bradford afbbd413a3 x86: baytrail: pci region 3 is not always mapped to end of ram
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF
and additional SDRAM is mapped from 0x100000000 and up.  There is a
physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses.
Because of this, PCI region 3 should only try to use up to the amount of
SDRAM or 0x80000000, which ever is less.

Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
2015-06-04 03:03:18 -06:00
..
cpu.c x86: Add a CPU driver for baytrail 2015-04-30 16:13:50 -06:00
early_uart.c x86: Add a x86_ prefix to the x86-specific PCI functions 2015-04-16 19:27:41 -06:00
fsp_configs.c x86: Add support for Intel Minnowboard Max 2015-02-06 12:07:39 -07:00
Kconfig x86: Add support for Intel Minnowboard Max 2015-02-06 12:07:39 -07:00
Makefile x86: Add a CPU driver for baytrail 2015-04-30 16:13:50 -06:00
pci.c x86: baytrail: pci region 3 is not always mapped to end of ram 2015-06-04 03:03:18 -06:00
valleyview.c x86: Remove unwanted MMC debugging 2015-04-29 21:02:32 -06:00