mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-15 09:27:35 +00:00
03a4504659
Originally, u-boot SPL will place the DTB directly after the kernel, but the size of the kernel does not include the BSS section, This means that u-boot SPL places the DTB in the kernel BSS section causing the DTB to be cleared by the kernel BSS initialisation. Moving the DTB in front of the kernel can avoid this error. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
166 lines
3.4 KiB
C
166 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017 Andes Technology Corporation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <flash.h>
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#include <image.h>
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#include <init.h>
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#include <net.h>
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#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
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#include <netdev.h>
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#endif
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#include <asm/global_data.h>
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#include <linux/io.h>
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#include <faraday/ftsmc020.h>
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#include <fdtdec.h>
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#include <dm.h>
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#include <spl.h>
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#include <mapmem.h>
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#include <hang.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Miscellaneous platform dependent initializations
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*/
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#if CONFIG_IS_ENABLED(LOAD_FIT) || CONFIG_IS_ENABLED(LOAD_FIT_FULL)
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#define ANDES_SPL_FDT_ADDR (CONFIG_TEXT_BASE - 0x100000)
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void spl_perform_fixups(struct spl_image_info *spl_image)
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{
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/*
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* Originally, u-boot-spl will place DTB directly after the kernel,
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* but the size of the kernel did not include the BSS section, which
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* means u-boot-spl will place the DTB in the kernel BSS section
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* causing the DTB to be cleared by kernel BSS initializtion.
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* Moving DTB in front of the kernel can avoid the error.
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*/
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if (ANDES_SPL_FDT_ADDR < 0) {
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printf("%s: CONFIG_TEXT_BASE needs to be larger than 0x100000\n",
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__func__);
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hang();
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}
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memcpy((void *)ANDES_SPL_FDT_ADDR, spl_image->fdt_addr,
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fdt_totalsize(spl_image->fdt_addr));
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spl_image->fdt_addr = map_sysmem(ANDES_SPL_FDT_ADDR, 0);
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}
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#endif
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
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return 0;
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}
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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int dram_init_banksize(void)
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{
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return fdtdec_setup_memory_banksize();
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}
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#if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH)
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int board_eth_init(struct bd_info *bd)
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{
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return ftmac100_initialize(bd);
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}
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#endif
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ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
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{
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return 0;
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}
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#define ANDES_HW_DTB_ADDRESS 0xF2000000
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void *board_fdt_blob_setup(int *err)
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{
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*err = 0;
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if (IS_ENABLED(CONFIG_OF_SEPARATE) || IS_ENABLED(CONFIG_OF_BOARD)) {
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if (fdt_magic((uintptr_t)gd->arch.firmware_fdt_addr) == FDT_MAGIC)
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return (void *)(ulong)gd->arch.firmware_fdt_addr;
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}
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if (fdt_magic(CONFIG_SYS_FDT_BASE) == FDT_MAGIC)
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return (void *)CONFIG_SYS_FDT_BASE;
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return (void *)ANDES_HW_DTB_ADDRESS;
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*err = -EINVAL;
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return NULL;
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}
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#ifdef CONFIG_SPL_BOARD_INIT
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void spl_board_init()
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{
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/* enable v5l2 cache */
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enable_caches();
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}
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#endif
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int smc_init(void)
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{
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int node = -1;
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const char *compat = "andestech,atfsmc020";
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void *blob = (void *)gd->fdt_blob;
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fdt_addr_t addr;
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struct ftsmc020_bank *regs;
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node = fdt_node_offset_by_compatible(blob, -1, compat);
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if (node < 0)
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return -FDT_ERR_NOTFOUND;
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addr = fdtdec_get_addr_size_auto_noparent(blob, node,
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"reg", 0, NULL, false);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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regs = (struct ftsmc020_bank *)(uintptr_t)addr;
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regs->cr &= ~FTSMC020_BANK_WPROT;
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return 0;
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}
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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smc_init();
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL
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void board_boot_order(u32 *spl_boot_list)
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{
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u8 i;
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u32 boot_devices[] = {
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#ifdef CONFIG_SPL_RAM_SUPPORT
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BOOT_DEVICE_RAM,
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#endif
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#ifdef CONFIG_SPL_MMC
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BOOT_DEVICE_MMC1,
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#endif
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};
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for (i = 0; i < ARRAY_SIZE(boot_devices); i++)
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spl_boot_list[i] = boot_devices[i];
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}
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#endif
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#ifdef CONFIG_SPL_LOAD_FIT
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int board_fit_config_name_match(const char *name)
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{
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/* boot using first FIT config */
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return 0;
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}
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#endif
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