mirror of
https://github.com/AsahiLinux/u-boot
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65cc0e2a65
The rest of the unmigrated CONFIG symbols in the CONFIG_SYS namespace do not easily transition to Kconfig. In many cases they likely should come from the device tree instead. Move these out of CONFIG namespace and in to CFG namespace. Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
350 lines
8.6 KiB
C
350 lines
8.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Keymile AG
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* Rainer Boschung <rainer.boschung@keymile.com>
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*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*/
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#include <event.h>
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#include <asm/cache.h>
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#include <asm/fsl_fdt.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_liodn.h>
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#include <asm/fsl_portals.h>
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#include <asm/fsl_serdes.h>
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#include <asm/immap_85xx.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <fdt_support.h>
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#include <fm_eth.h>
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#include <hwconfig.h>
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#include <image.h>
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#include <linux/compiler.h>
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#include <net.h>
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#include <netdev.h>
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#include <vsc9953.h>
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#include "../common/common.h"
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#include "../common/qrio.h"
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DECLARE_GLOBAL_DATA_PTR;
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static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
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int checkboard(void)
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{
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printf("Board: Hitachi Power Grids %s\n", KM_BOARD_NAME);
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return 0;
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}
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#define RSTRQSR1_WDT_RR 0x00200000
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#define RSTRQSR1_SW_RR 0x00100000
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int board_early_init_f(void)
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{
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struct fsl_ifc ifc = {(void *)CFG_SYS_IFC_ADDR, (void *)NULL};
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ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
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bool cpuwd_flag = false;
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/* board specific IFC configuration: increased bus turnaround time */
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setbits_be32(&ifc.gregs->ifc_gcr, 8 << IFC_GCR_TBCTL_TRN_TIME_SHIFT);
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/* configure mode for uP reset request */
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qrio_uprstreq(UPREQ_CORE_RST);
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/* board only uses the DDR_MCK0, so disable the DDR_MCK1 */
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setbits_be32(&gur->ddrclkdr, 0x40000000);
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/* set reset reason according CPU register */
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if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
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RSTRQSR1_WDT_RR)
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cpuwd_flag = true;
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qrio_cpuwd_flag(cpuwd_flag);
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/* clear CPU bits by writing 1 */
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setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
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/* configure PRST lines for the application: */
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/*
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* ETHSW_DDR_RST:
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* reset at power-up and unit reset only and enable WD on it
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*/
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qrio_prstcfg(KM_ETHSW_DDR_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_ETHSW_DDR_RST, true);
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/*
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* XES_PHY_RST:
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* reset at power-up and unit reset only and enable WD on it
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*/
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qrio_prstcfg(KM_XES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_XES_PHY_RST, true);
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/*
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* ES_PHY_RST:
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* reset at power-up and unit reset only and enable WD on it
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*/
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qrio_prstcfg(KM_ES_PHY_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_ES_PHY_RST, true);
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/*
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* EFE_RST:
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* reset at power-up and unit reset only and enable WD on it
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*/
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qrio_prstcfg(KM_EFE_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_EFE_RST, true);
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/*
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* BFTIC4_RST:
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* reset at power-up and unit reset only and enable WD on it
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*/
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qrio_prstcfg(KM_BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_BFTIC4_RST, true);
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/*
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* DPAXE_RST:
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* reset at power-up and unit reset only and enable WD on it
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*/
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qrio_prstcfg(KM_DPAXE_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_DPAXE_RST, true);
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/*
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* PEXSW_RST:
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* reset at power-up and unit reset only, deassert reset w/o WD
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*/
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qrio_prstcfg(KM_PEXSW_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_prst(KM_PEXSW_RST, false, false);
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/*
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* PEXSW_NT_RST:
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* reset at power-up and unit reset only, deassert reset w/o WD
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*/
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qrio_prstcfg(KM_PEXSW_NT_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_prst(KM_PEXSW_NT_RST, false, false);
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/*
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* BOBCAT_RST:
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* reset at power-up and unit reset only, deassert reset w/o WD
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*/
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qrio_prstcfg(KM_BOBCAT_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_prst(KM_BOBCAT_RST, false, false);
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/*
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* FEMT_RST:
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* reset at power-up and unit reset only and enable WD
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*/
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qrio_prstcfg(KM_FEMT_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_FEMT_RST, true);
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/*
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* FOAM_RST:
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* reset at power-up and unit reset only and enable WD
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*/
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qrio_prstcfg(KM_FOAM_RST, PRSTCFG_POWUP_UNIT_RST);
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qrio_wdmask(KM_FOAM_RST, true);
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return 0;
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}
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int board_early_init_r(void)
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{
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int ret = 0;
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const unsigned int flashbase = CFG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CFG_SYS_FLASH_BASE_PHYS,
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MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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set_liodns();
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setup_qbman_portals();
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qrio_set_leds();
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/* enable Application Buffer */
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qrio_enable_app_buffer();
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return ret;
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}
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unsigned long get_serial_clock(unsigned long dummy)
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{
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return (gd->bus_clk / 2);
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}
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static int kmcent2_misc_init_f(void *ctx, struct event *event)
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{
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/* configure QRIO pis for i2c deblocking */
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i2c_deblock_gpio_cfg();
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/*
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* CFE_RST (front phy):
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* reset at power-up, unit and core reset, deasset reset w/o WD
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*/
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qrio_prstcfg(KM_CFE_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
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qrio_prst(KM_CFE_RST, false, false);
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/*
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* ZL30158_RST (PTP clock generator):
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* reset at power-up only, deassert reset and enable WD on it
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*/
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qrio_prstcfg(KM_ZL30158_RST, PRSTCFG_POWUP_RST);
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qrio_prst(KM_ZL30158_RST, false, false);
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/*
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* ZL30364_RST (EEC generator):
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* reset at power-up only, deassert reset and enable WD on it
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*/
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qrio_prstcfg(KM_ZL30364_RST, PRSTCFG_POWUP_RST);
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qrio_prst(KM_ZL30364_RST, false, false);
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return 0;
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}
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EVENT_SPY(EVT_MISC_INIT_F, kmcent2_misc_init_f);
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#define USED_SRDS_BANK 0
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#define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100
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#define BRG01_IOCLK12 0x02000000
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#define EC2_GTX_CLK125 0x08000000
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int misc_init_r(void)
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{
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serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85xx_SCFG;
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ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85xx_GUTS_ADDR;
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/* check SERDES bank 0 reference clock */
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u32 actual = in_be32(®s->bank[USED_SRDS_BANK].pllcr0);
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if (actual & SRDS_PLLCR0_POFF)
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printf("Warning: SERDES bank %u pll is off\n", USED_SRDS_BANK);
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if ((actual & SRDS_PLLCR0_RFCK_SEL_MASK) != EXPECTED_SRDS_RFCK) {
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printf("Warning: SERDES bank %u expects %sMHz clock, is %sMHz\n",
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USED_SRDS_BANK,
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serdes_clock_to_string(EXPECTED_SRDS_RFCK),
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serdes_clock_to_string(actual));
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}
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/* QE IO clk : BRG01 is used over clk12 for HDLC clk (20 MhZ) */
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out_be32(&scfg->qeioclkcr,
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in_be32(&scfg->qeioclkcr) | BRG01_IOCLK12);
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ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN,
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CONFIG_PIGGY_MAC_ADDRESS_OFFSET);
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/* Fix polarity of Card Detect and Write Protect */
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out_be32(&gur->sdhcpcr, 0xFFFFFFFF);
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/*
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* EC1 is disabled in our design, so we must explicitly set GTXCLKSEL
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* to EC2
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*/
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out_be32(&scfg->emiiocr, in_be32(&scfg->emiiocr) | EC2_GTX_CLK125);
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return 0;
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}
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int hush_init_var(void)
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{
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ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
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return 0;
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}
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int last_stage_init(void)
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{
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const char *kmem;
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/* DIP switch support on BFTIC */
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struct bfticu_iomap *bftic4 =
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(struct bfticu_iomap *)SYS_BFTIC_BASE;
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u8 dip_switch = in_8((u8 *)&bftic4->mswitch) & BFTICU_DIPSWITCH_MASK;
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if (dip_switch != 0) {
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/* start bootloader */
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puts("DIP: Enabled\n");
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env_set("actual_bank", "0");
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}
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set_km_env();
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/*
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* bootm_size is used to fixup the FDT memory node
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* set it to kernelmem that has the same value
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*/
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kmem = env_get("kernelmem");
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if (kmem)
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env_set("bootm_size", kmem);
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return 0;
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}
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void fdt_fixup_fman_mac_addresses(void *blob)
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{
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int node, ret;
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char path[24];
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unsigned char mac_addr[6];
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/*
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* Just the fm1-mac5 must be set by us, u-boot handle the 2 others,
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* get the mac addr from env
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*/
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if (!eth_env_get_enetaddr_by_index("eth", 4, mac_addr)) {
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printf("eth4addr env variable not defined\n");
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return;
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}
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/* local management port */
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strcpy(path, "/soc/fman/ethernet@e8000");
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node = fdt_path_offset(blob, path);
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if (node < 0) {
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printf("no %s\n", path);
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return;
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}
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ret = fdt_setprop(blob, node, "local-mac-address", mac_addr, 6);
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if (ret) {
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printf("%s\n\terror setting local-mac-address property\n",
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path);
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}
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}
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = env_get_bootm_low();
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size = env_get_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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fdt_fixup_liodn(blob);
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fdt_fixup_fman_mac_addresses(blob);
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if (hwconfig("qe-tdm"))
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fdt_del_diu(blob);
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return 0;
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}
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/* DIC26_SELFTEST GPIO used to start factory test sw */
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#define SELFTEST_PORT QRIO_GPIO_A
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#define SELFTEST_PIN 0
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int post_hotkeys_pressed(void)
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{
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qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
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return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
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}
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